17.6.2 Deadman Timer Preclear
| Name: | DMTPRECLR |
| Offset: | 0x10 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| STEP1[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 15:8 – STEP1[7:0] Pre-Clear Enable bit when write pattern is:
| Value | Description |
|---|---|
| 01000000 | Enables the Deadman Timer Pre-Clear (STEP 1). |
| all other write patterns | Sets
DMTSTAT.BAD1 flag to ‘1’.Note: Bits 15:8 are cleared
when a DMT reset event occurs. STEP1 is also cleared if DMTCLR.STEP2 is
loaded with the correct value in the correct
sequence. |