22.8.9 Interrupt Pending
An interrupt that handles several channels must consult the INTPEND register to find out which channel number has priority (ignoring/filtering each channel that has its own interrupt line). An interrupt dedicated to only one channel must not use the INTPEND register.
| Name: | INTPEND |
| Offset: | 0x20 |
| Reset: | 0x0000 |
| Property: | - |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| PEND | BUSY | FERR | CRCERR | SUSP | TCMPL | TERR | |||
| Access | R | R | R | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ID[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bit 15 – PEND Pending
This bit will read ‘1’ when the channel
selected by Channel ID field (ID) is pending.
Bit 14 – BUSY Busy
This bit will read ‘1’ when the channel
selected by Channel ID field (ID) is busy.
Bit 13 – FERR Fetch Error
This bit will read ‘1’ when the channel
selected by Channel ID field (ID) fetched an invalid descriptor.
Bit 12 – CRCERR CRC Error
1’ when the channel selected by Channel ID field (ID) has a
CRC Error Status Flag bit set, and is set when the CRC monitor detects data
corruption. Writing a ‘0’ to this bit has no
effect.
Writing a ‘1’ to this bit will clear it. It will
also clear the corresponding flag in the Channel n Interrupt Flag Status and
Clear register (CHINTFLAGn), where n is determined by the Channel ID bit field
(ID).
Bit 10 – SUSP Channel Suspend
This bit will read ‘1’ when the channel
selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a ‘0’ to this bit has no
effect.
Writing a ‘1’ to this bit will clear it. It will also clear the
corresponding flag in the Channel n Interrupt Flag Status and Clear register
(CHINTFLAGn), where n is determined by the Channel ID bit field (ID).
Bit 9 – TCMPL Transfer Complete
This bit will read ‘1’ when the channel
selected by Channel ID field (ID) has pending Transfer Complete interrupt.
Writing a ‘0’ to this bit has no
effect.
Writing a ‘1’ to this bit will clear it. It will also clear the
corresponding flag in the Channel n Interrupt Flag Status and Clear register
(CHINTFLAGn), where n is determined by the Channel ID bit field (ID).
Bit 8 – TERR Transfer Error
This bit will read ‘1’ when the channel
selected by Channel ID field (ID) has pending Transfer Error interrupt.
Writing a ‘0’ to this bit has no
effect.
Writing a ‘1’ to this bit will clear it.
It will also clear the corresponding flag in the Channel n Interrupt Flag Status
and Clear register (CHINTFLAGn), where n is determined by the Channel ID bit
field (ID).
Bits 4:0 – ID[4:0] Channel ID
These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP), Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new channel (with channel number less than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources. When no pending channels interrupts are available, these bits will always return zero value when read.
When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.