12.13.9 CoreSight ROM Table Entry x

Name: ENTRY
Offset: 0x1000 + n*0x04 [n=0..1]
Reset: 0xxxxxx00x
Property: PAC Write-Protection

Bit 3130292827262524 
 ADDOFF[19:12] 
Access RRRRRRRR 
Reset xxxxxxxx 
Bit 2322212019181716 
 ADDOFF[11:4] 
Access RRRRRRRR 
Reset xxxxxxxx 
Bit 15141312111098 
 ADDOFF[3:0]     
Access RRRR 
Reset xxxx 
Bit 76543210 
       FMTEPRES 
Access RR 
Reset 1x 

Bits 31:12 – ADDOFF[19:0] Address Offset

The base address of the component, relative to the base address of this ROM table.

Bit 1 – FMT Format

Always reads as '1', indicating a 32-bit ROM table.

Bit 0 – EPRES Entry Present

This bit indicates whether an entry is present at this location in the ROM table.

This bit is set at power-up if the device is not protected indicating that the entry is not present.

This bit is cleared at power-up if the device is not protected indicating that the entry is present.