8 Product Memory Mapping Overview

Figure 8-1. Product Mapping
Note:
  1. Access attempts to any unimplemented memory location generates a bus error.
  2. The PUKCC space is fixed as non-cacheable and bufferable.
  3. The QSPI space “cacheable and bufferable” attribute is controlled using CFGCON1.QSCHE_EN.
Table 8-1. Device Configuration Map
Register NameReset value from NVR memory?Writable in User Mode?Corresponding Write Lock Bit(s)Purpose
System Configuration
CFGCON0(L)0x4400_0000XXCFGLOCK[1:0] Misc. System Configuration
CFGCON1(L)0x4400_0010XXCFGLOCK[1:0]Misc. System Configuration
CFGCON2(L)0x4400_0020XXCFGLOCK[1:0]Misc. System Configuration
CFGCON30x4400_0030 —XCFGLOCK[1:0]Misc. System Configuration
CFGCON4(L)0x4400_0040X XCFGLOCK[1:0]Misc. System Configuration
CFGPGQOS0x4400_0050 —XCFGCON0.PGLOCKBus Matrix Permission Groups
CFGPCLKGEN10x4400_0060—XCFGLOCK[1:0]Peripheral Clock Gen Reg-1
CFGPCLKGEN20x4400_0070—XCFGLOCK[1:0]Peripheral Clock Gen Reg-2
CFGPCLKGEN30x4400_0080—XCFGLOCK[1:0]Peripheral Clock Gen Reg-3
ID20x4400_0090X—N/A- Read Only32-bit Device ID
USER_ID(L)0x4400_00A0XX CFGLOCK[1:0]16-bit User ID
SYSKEY0x4400_00B0 —XSequenceSystem Lock feature
PMD10x4400_00C0—XCFGCON0.PMDLOCKPeripheral Module Disable
PMD20x4400_00D0—XCFGCON0.PMDLOCKPeripheral Module Disable
PMD30x4400_00E0—XCFGCON0.PMDLOCKPeripheral Module Disable
Boot Configuration

BCFG0

0x4400_0200

X—NonePre-boot user configuration
Note:
  1. Registers marked with (L) are loadable from Flash, and they can be controlled by software after the boot with the correct unlock sequence.
  2. ID Register is a JTAB ID register, maintained for legacy reasons. The actual external-facing ID register is DSU.DID register. See DID register in the Device Service Unit (DSU) from Related Links.
Table 8-2. CM4 System Components Register Offset Map
PeripheralTA ClockSize (Bytes)Virtual AddressPhysical Address
ABRV.DescriptionStartEndStartEnd

CM4 System Components accessible via CM4 PPB Bus

(Only DAP and CM4 can access the registers)

Base Address

0xE000_0000

Base Address

0xE000_0000

ITM Inst. TMSYS_CLK4 KB0000_00000000_0FFF0000_00000000_0FFF
DWTData WTSYS_CLK4 KB0000_10000000_1FFF0000_10000000_1FFF
FPBFlash PBSYS_CLK4 KB0000_20000000_2FFF0000_20000000_2FFF
RSVDReserved—4 KB*n0000_30000000_DFFF0000_30000000_DFFF
SCSSys. CSSYS_CLK4 KB0000_E0000000_EFFF0000_E0000000_EFFF
RSVDReserved—4 KB*n0000_F0000003_FFFF0000_F0000003_FFFF
TPIUTrace PIUSYS_CLK4 KB0004_00000004_0FFF0004_00000004_0FFF
ETMETMSYS_CLK4 KB0004_10000004_1FFF0004_10000004_1FFF
ETBETBSYS_CLK4 KB0004_20000004_2FFF0004_20000004_2FFF
RSVDReserved—4 KB*n0004_3000000F_EFFF0004_3000000F_EFFF
CROMCSight ROMSYS_CLK4 KB000F_F000000F_FFFF000F_F000000F_FFFF
RSVDReserved—4 KB*n0010_0000FFFF_FFFF0010_0000FFFF_FFFF
Note:
  1. All system and debug components carry a unique ID accessible via its own register space.
  2. The DAP derives the base address of the components from CROM entry values.
  3. Component Base address = CROM Base address + CROM Entry value.
  4. Core sight ROM entries are not provided in this document.
  5. Refer to CM4F documentation for details on each component register space (developer.arm.com/documentation/ddi0439/b/System-Control/Register-summary).