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PIC32CX-BZ2 and WBZ45 Family Data Sheet
Introduction
PIC32CX-BZ2 SoC Family Features
Operating Conditions
Core: 64 MHz ARM® Cortex®-M4
Memories
System
Supported Connectivity Standards
Power Supply
2.4 GHz RF Transceiver
Bluetooth®
802.15.4/Zigbee® Modulation Scheme
Proprietary
High Performance Peripherals
System Peripherals
Security
Oscillators
I/O
Package
WBZ45 Module Features
WBZ45 Module Variants
Antenna
Clock Management
System Peripheral, Advanced Analog and Security
Package and Operating Conditions
Certifications
Acronyms and Abbreviations
1 Ordering Information
1.1 PIC32CX-BZ2 SoC Ordering Information
1.2 WBZ45 Module Ordering Information
2 Configuration Summary
3 PIC32CX-BZ2 SoC Description
3.1 PIC32CX-BZ2 SoC Block Diagram
3.2 Pinout Diagram
4 WBZ45 Module Description
4.1 Pinout Diagram
4.2 Basic Connection Requirement
4.3 WBZ45 Module Placement Guidelines
4.4 WBZ45 Module Routing Guidelines
4.5 WBZ45 Module RF Considerations
4.6 WBZ45 Module Antenna Considerations
4.7 WBZ45 Module Reflow Profile Information
4.8 WBZ45 Module Assembly Considerations
5 Pinout and Signal Descriptions List
6 I/O Ports and Peripheral Pin Select (PPS)
6.1 Control Registers
6.2 Peripheral Pin Select (PPS)
6.3 Function Priority for Device Pins
6.4 I/O Ports Control Registers
6.5 Operation in Power Saving Modes
6.6 Results of Various Resets
7 Power Subsystem
7.1 Block Diagram
7.2 Voltage Regulators
7.3 Power Supply Modes
7.4 Typical Power Supply Connection for SoC
7.5 Typical Power Supply Connection for Module
7.6 Power-Up Sequence
8 Product Memory Mapping Overview
9 Prefetch Cache (PCHE)
9.1 Introduction
9.2 Features
9.3 Overview
9.4 Prefetch Behavior
9.5 Configurations
9.6 Predictive Prefetch Behavior
9.7 Coherency Support
9.8 Effects of Reset
9.9 Error Conditions
9.10 Operation in Power-saving Modes
9.11 Register Summary (PCHE)
9.12 Register Description
10 Processor and Architecture
10.1 Cortex M4 Processor
10.2 Nested Vector Interrupt Controller (NVIC)
10.3 High-Speed Bus System
11 Cortex M Cache Controller (CMCC)
11.1 Overview
11.2 Features
11.3 Block Diagram
11.4 Signal Description
11.5 Product Dependencies
11.6 Functional Description
11.7 DEBUG Mode
11.8 RAM Properties
11.9 Register Summary
11.10 Register Description
12 Device Service Unit (DSU)
12.1 Overview
12.2 Features
12.3 Block Diagram
12.4 Signal Description
12.5 Product Dependencies
12.6 Debug Operation
12.7 Chip Erase
12.8 Programming
12.9 Intellectual Property Protection
12.10 Device Identification
12.11 Functional Description
12.12 DSU Register Summary
12.13 Register Description
13 Clock and Reset Unit (CRU)
13.1 Overview
13.2 Features
13.3 Block Diagram
13.4 System and Peripheral Clock Generation (CLKGEN)
13.5 Idle Mode
13.6 Dream Mode
13.7 FRCDIV
13.8 RFPLL Wrapper
13.9 Start-up Considerations
13.10 Fail-Safe Clock Monitor
13.11 Fast RC Oscillator
13.12 Secondary Oscillator
13.13 Low Power RC Oscillator (LPRC)
13.14 Reference Clock Generator
13.15 Resets
13.16 Register Summary
13.17 Register Description
14 RAM Error Correction Code (RAMECC)
14.1 Overview
14.2 Features
14.3 Block Diagram
14.4 Signal Description
14.5 Product Dependencies
14.6 Functional Description
14.7 Register Summary - RAMECC
14.8 Register Description
15 Power Management Unit (PMU)
15.1 Overview
15.2 Power Modes
15.3 PMU Register Summary
15.4 Deep Sleep Control Register
Deep Sleep Control Register
16 Watchdog Timer (WDT)
16.1 Overview
16.2 Features
16.3 Applications
16.4 Block Diagram
16.5 Configuration
16.6 Register Summary - WDT
16.7 Register Description
17 Deadman Timer (DMT)
17.1 Overview
17.2 Features
17.3 Block Diagram
17.4 DMT Operation
17.5 Register Summary
17.6 Register Description
18 System Configuration and Register Locking (CFG)
18.1 Overview
18.2 Applications
18.3 CFG Register Summary
18.4 Register Description
19 Register Locking
19.1 System Lock Register
19.2 Register Summary
19.3 Register Description
20 Peripheral Module Disable Register (PMD)
20.1 Overview
20.2 Enabling Peripherals
20.3 Registers and Bits
20.4 PMD Register
20.5 PMDx Initialization Values by Variant Name
21 Real-Time Counter and Calendar (RTCC)
21.1 Overview
21.2 Features
21.3 Block Diagram
21.4 Signal Description
21.5 Product Dependencies
21.6 Functional Description
21.7 Register Summary - Mode 0 - 32-Bit Counter
21.8 Register Description - Mode 0 - 32-Bit Counter
21.9 Register Summary - Mode 1 - 16-Bit Counter
21.10 Register Description - Mode 1 - 16-Bit Counter
21.11 Register Summary - Mode 2 - Clock/Calendar
21.12 Register Description - Mode 2 - Clock/Calendar
22 Direct Memory Access Controller (DMAC)
22.1 Overview
22.2 Features
22.3 Block Diagram
22.4 Signal Description
22.5 Product Dependencies
22.6 Functional Description
22.7 DMAC Register Summary
22.8 Register Description
22.9 DMAC Register Summary (SRAM)
22.10 Register Description - SRAM
23 External Interrupt Controller (EIC)
23.1 Overview
23.2 Features
23.3 Block Diagram
23.4 Signal Description
23.5 Product Dependencies
23.6 Functional Description
23.7 EIC Register Summary
23.8 Register Description
24 Flash Memory
24.1 Overview
24.2 Features
24.3 Functional Block Diagram
24.4 Flash Memory Addressing
24.5 Memory Configuration
24.6 Boot Flash Memory (BFM) Partitions
24.7 Program Flash Memory (PFM) Partitions
24.8 Error Correcting Code (ECC) and Flash Programming
24.9 Interrupts
24.10 Error Detection
24.11 NVMKEY Register Unlocking Sequence
24.12 Word Programming
24.13 Quad Word Programming
24.14 Row Programming
24.15 Page Erase
24.16 Program Flash Memory (PFM) Erase
24.17 Pre-Program
24.18 Device Code Protection bit (CP)
24.19 Operation in Power-Saving Modes
24.20 Operation in Debug Mode
24.21 Effects of Various Resets
24.22 Control Registers
25 Integrity Check Monitor (ICM)
25.1 Overview
25.2 Features
25.3 Block Diagram
25.4 Signal Description
25.5 Product Dependencies
25.6 Functional Description
25.7 Register Summary - ICM
25.8 Register Description
26 Peripheral Access Controller (PAC)
26.1 Overview
26.2 Features
26.3 Block Diagram
26.4 Product Dependencies
26.5 Functional Description
26.6 Register Summary
26.7 Register Description
27 Frequency Meter (FREQM)
27.1 Overview
27.2 Features
27.3 Block Diagram
27.4 Signal Description
27.5 Product Dependencies
27.6 Functional Description
27.7 Register Summary - FREQM
27.8 Register Description
28 Event System (EVSYS)
28.1 Overview
28.2 Features
28.3 Block Diagram
28.4 Product Dependencies
28.5 Functional Description
28.6 Register Summary
28.7 Register Description
29 Serial Communication Interface (SERCOM)
29.1 Overview
29.2 Features
29.3 Block Diagram
29.4 Signal Description
29.5 Product Dependencies
29.6 Functional Description
30 SERCOM Synchronous and Asynchronous Receiver and Transmitter (SERCOM USART)
30.1 Overview
30.2 USART Features
30.3 Block Diagram
30.4 Signal Description
30.5 Product Dependencies
30.6 Functional Description
30.7 Register Summary
30.8 Register Description
31 SERCOM Serial Peripheral Interface (SERCOM SPI)
31.1 Overview
31.2 Features
31.3 Block Diagram
31.4 Signal Description
31.5 Product Dependencies
31.6 Functional Description
31.7 Register Summary
31.8 Register Description
32 SERCOM Inter-Integrated Circuit (SERCOM I2C)
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 Signal Description
32.5 Product Dependencies
32.6 Functional Description
32.7 Register Summary - I2C Client
32.8 Register Description - I2C Client
32.9 Register Summary - I2C Host
32.10 Register Description – I2C Host
33 Quad Serial Peripheral Interface (QSPI)
33.1 Overview
33.2 Features
33.3 Block Diagram
33.4 GUID-761A0CEC-666A-4526-AC43-5AADC7F25FC2-high.svg
33.5 Signal Description
33.6 Product Dependencies
33.7 Functional Description
33.8 Register Summary
33.9 Register Description
34 Configurable Custom Logic (CCL)
34.1 Overview
34.2 Features
34.3 Block Diagram
34.4 Signal Description
34.5 Product Dependencies
34.6 Functional Description
34.7 Register Summary
34.8 Register Description
35 True Random Number Generator (TRNG)
35.1 Overview
35.2 Features
35.3 Block Diagram
35.4 Signal Description
35.5 Product Dependencies
35.6 Functional Description
35.7 Register Summary
35.8 Register Description
36 Advanced Encryption Standard (AES)
36.1 Overview
36.2 Features
36.3 Block Diagram
36.4 Signal Description
36.5 Product Dependencies
36.6 Functional Description
36.7 Register Summary
36.8 Register Description
37 Public Key Cryptography Controller (PUKCC)
37.1 Overview
37.2 Product Dependencies
37.3 Functional Description
38 Analog-to-Digital Converter (ADC)
38.1 Overview
38.2 ADC Operation
38.3 ADC Module Configuration
38.4 Additional ADC Functions
38.5 Interrupts
38.6 Power-Saving Modes of Operation
38.7 Effects of Reset
38.8 Transfer Function
38.9 ADC Sampling Requirements
38.10 Connection Considerations
38.11 Register Description
39 Analog Comparators (AC)
39.1 Overview
39.2 Features
39.3 Block Diagram
39.4 Product Dependencies
39.5 Functional Description
39.6 Register Summary
39.7 Register Description
40 Timer/Counter (TC)
40.1 Overview
40.2 Features
40.3 Block Diagram
40.4 Signal Description
40.5 Product Dependencies
40.6 Functional Description
40.7 Register Description
41 Timer/Counter for Control Applications (TCC)
41.1 Overview
41.2 Features
41.3 Block Diagram
41.4 Signal Description
41.5 Product Dependencies
41.6 Functional Description
41.7 Register Summary
41.8 Register Description
41.9 GUID-9F6D40E9-5BEB-4F82-8668-E50472BA04BF-high.svg
42 Zigbee® Bluetooth® Radio Subsystem
42.1 Overview
42.2 Features
42.3 Wireless Subsystem Top Level Diagram
42.4 Bluetooth Link Controller
42.5 Zigbee/Proprietary Data Rate Link Controller
42.6 Radio Arbiter
42.7 RF Physical Layer
42.8 Frequency Synthesizer
42.9 RFLDO
43 Electrical Characteristics
43.1 Absolute Maximum Electrical Characteristics
43.2 DC Electrical Characteristics
43.3 Thermal Specifications
43.4 Power Supply Electrical Specifications
43.5 Active Current Consumption DC Electrical Specifications (85°C)
43.6 Active Current Consumption DC Electrical Specifications (125°C)
43.7 Idle Current Consumption DC Electrical Specifications (85°C)
43.8 Idle Current Consumption DC Electrical Specifications (125°C)
43.9 Sleep Current Consumption DC Electrical Specifications (85°C)
43.10 Sleep Current Consumption DC Electrical Specifications (125°C)
43.11 Deep Sleep Current Consumption DC Electrical Specifications (85°C)
43.12 Deep Sleep Current Consumption DC Electrical Specifications (125°C)
43.13 XDS (Extreme Deep Sleep) Current Consumption DC Electrical Specifications (85°C)
43.14 XDS (Extreme Deep Sleep) Current Consumption DC Electrical Specifications (125°C)
43.15 Wake-Up Timing from Low Power Modes AC Electrical Specifications
43.16 I/O PIN AC/DC Electrical Specifications
43.17 External XTAL and Clock AC Electrical Specifications
43.18 XOSC32 AC Electrical Specifications
43.19 Low Power Internal 32 kHz RC Oscillator AC Electrical Specifications
43.20 FRC AC Electrical Specifications
43.21 Frequency AC Electrical Specifications
43.22 ADC Electrical Specifications
43.23 Comparator AC Electrical Specifications
43.24 SPI Module Electrical Specifications
43.25 UART AC Electrical Specifications
43.26 I2C Module Electrical Specifications
43.27 QSPI Module Electrical Specifications
43.28 TCx Timer Capture Module AC Electrical Specifications
43.29 TCCx Timer Capture Module AC Electrical Specifications
43.30 FLASH NVM AC Electrical Specifications
43.31 Frequency Meter AC Electrical Specifications
43.32 Bluetooth® Low Energy RF Characteristics
43.33 Zigbee RF Characteristics
44 Packaging Information
44.1 PIC32CX1012BZ25048 SoC Packaging Information
44.2 PIC32CX1012BZ24032 SoC Packaging Information
44.3 WBZ451 Module Packaging Information
44.4 WBZ450 Module Packaging Information
44.5 WBZ451H Module Packaging Information
45 Appendix A: Regulatory Approval
45.1 United States
45.2 Canada
45.3 Europe
45.4 Japan
45.5 Korea
45.6 Taiwan
45.7 China
45.8 UKCA (UK Conformity Assessed)
45.9 Other Regulatory Information
46 Appendix B: Acronyms and Abbreviations
47 Document Revision History
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature