67.3 Recommended Operating Conditions

Table 67-3. Recommended Operating Conditions on Power Supply Inputs
Power Input Parameters Conditions Min Max Unit
VDDIN33 VDDOUT25 regulator input, USB interface I/O lines and Main crystal oscillator power supply(1) – 3.00 3.60 V
VDDANA VDDANA I/O lines, A/D Converter, and OTP memory power supply(1) – 3.00 3.60 V
VDDCORE Core Logic (processor, peripherals, memories, UTMI logic, etc.) power supply

fCPU ≤ 600 MHz, fMCK ≤ 200 MHz

fCPU ≤ 800 MHz, fMCK ≤ 266 MHz

1.04

1.14

1.21

1.21

V
VDDIOM SDRAM I/O lines power supply

DDR2-SDRAM

DDR3-SDRAM

DDR3L-SDRAM

1.70

1.425

1.283

1.90

1.575

1.450

V
VDDNF NAND Flash I/O lines power supply(2) – 1.70 3.60 V
VDDIOP0 VDDIOP0 I/O lines power supply(2) – 1.70 3.60 V
VDDIOP1 VDDIOP1 I/O lines power supply(2) – 1.70 3.60 V
VDDIOP2 VDDIOP2 I/O lines power supply(2) – 1.70 3.60 V
VDDQSPI VDDQSPI I/O lines power supply(2) – 1.70 3.60 V
VDDLVDS LVDS PHY and VDDLVDS I/O lines power supply(2)(3) – 1.70 3.60 V
VDDMIPI MIPI PHY and I/O lines power supply(4) – 2.25 2.75 V
VDDBU Backup domain power supply – 1.6 3.60 V
tR_VDD Power supply slope at power-up – 0.2 20 mV/µs
tF_VDD Power supply slope at power-down – –20 –1(5) mV/µs
Note:
  1. VDDANA and VDDIN33 are powered from one single source: V(VDDANA,VDDIN33) ≤ ±50mV.
  2. Supply range restrictions apply when using the digital peripheral timing characteristics. See I/O Characteristics.
  3. When the LVDS PHY is used, VDDLVDS must be connected to VDDOUT25.
  4. VDDMIPI must be connected to VDDOUT25.
  5. For VDDBU, this value is 0 mV/µs.
Table 67-4. Recommended Operating Conditions on Input Pins(1)
Symbol Parameters Conditions Min Max Unit
VIN Input line voltage range on inputs(2)(3) – -0.3 VDD+0.3 V
IIN DC current injection on input (4)(5) – – ±0.2 mA
ITOT_INJ Total current injection per power rail or ground rail (6) – – ±2 mA
Note:
  1. In this table, VDD refers to the voltage of the associated power rail of the I/O line, as defined in the Pin Description table. Ex: for PA2, VDD refers to VDDIOP0.
  2. Input voltages VIN ≤ 0V or VIN ≥ VDD lead to negative or positive current injection on inputs.
  3. For analog inputs (PA[31:24]), input voltages VIN ≥ min(VDDANA, VADVREFP) lead to saturated A/D conversion to 0xFFF.
  4. Current injection on A/D converter analog inputs (PA[31:24]) may degrade the analog performance of the corresponding channel or the analog performance of other analog channels.
  5. High frequency current injection must be limited to avoid propagating high frequency signals to internal sensitive analog circuits (oscillators, regulators, etc.). One common use case of high frequency current injection occurs when a digital input pin suffers overshoots and/or undershoots from a poorly adapted transmission line (PCB trace with signal reflections, for example). These cases should be cured by appropriate source series resistor termination. Special attention must be paid to high speed interfaces (Gigabit Ethernet MAC I/F, SD Card or e.MMC I/F, QSPI I/F, etc.).
  6. Corresponds to the sum of the positive currents into one power rail and respectively to the sum of the negative currents into one ground rail, as defined in the Pin Description table.
Table 67-5. Recommended Operating Conditions on Internal Clocks
Symbol Parameters Conditions Min Max Unit

fCPU_CLK

 Processor clock (CPU_CLK) frequency VDDCORE ≥ 1.14V – 800 MHz

VDDCORE ≥ 1.04V

 – 600 MHz

fMCK

 Main system bus clock (MCK) frequency VDDCORE ≥ 1.14V – 266 MHz
VDDCORE ≥ 1.04V – 200 MHz
Table 67-6. Recommended Operating Conditions on SDRAM Interface
Symbol Parameters Conditions Min Max Unit
fSDRAM_CLK SDRAM clock frequency VDDCORE ≥ 1.14V – – –
DDR2-SDRAM 125 266 –
DDR3(L)-SDRAM (DLL ON)(1) 266 – –
DDR3(L)-SDRAM (DLL OFF)(2) – 200 –
fSDRAM_CLK SDRAM Clock frequency VDDCORE ≥ 1.04V – – –
DDR2-SDRAM 125 200 –
DDR3(L)-SDRAM (DLL OFF)(2) – 200 –
Note:
  1. According to the JEDEC specification, DDR3(L) “DLL On mode” is supported for clock frequencies of 300 MHz and above. Most memory suppliers accept operations down to 266 MHz. Contact the memory supplier for further details.
  2. According to the JEDEC specification, DDR3(L) “DLL Off mode” is supported for clock frequencies up to 125 MHz. Most memory suppliers accept operations up to 200 MHz. Contact the memory supplier for further details.
Table 67-7. Recommended Thermal Operating Conditions
Symbol Parameter Conditions Min Max Unit
TA Ambient temperature range SAM9X7x-I devices -40 85 °C
SAM9X7x-V devices -40 105 °C
TJ Junction temperature range – -40 125 °C
Table 67-8. Package Characteristics ─ SAM9X7x-I Devices
Symbol Parameter Conditions Min Max Unit
RJA Junction-to-ambient thermal resistance – 38 °C/W
RJC Junction-to-case thermal resistance – 16 °C/W
RJB Junction-to-board thermal resistance – 31 °C/W
ΨJ-top Junction-to-case thermal resistance – 0.57 °C/W
Note: The package characteristics in the table above are provided according to the JEDEC JESD51-2 standard with the 2s2p board and 0m/s air flow. These parameters do not characterize the package alone but rather the package mounted on the JEDEC-defined PCB. Different applications conditions (PCB stack-up and size, air flow speed, etc.) may result in different thermal characteristics.
Table 67-9. Package Characteristics ─ SAM9X7x-V Devices
Symbol Parameter Conditions Min Max Unit
RJA Junction-to-ambient thermal resistance – 33 °C/W
RJC Junction-to-case thermal resistance – 12 °C/W
RJB Junction-to-board thermal resistance – 26 °C/W
ΨJ-top Junction-to-case thermal resistance – 0.45 °C/W
Note: The package characteristics in the table above are provided according to the JEDEC JESD51-2 standard with the 2s2p board and 0m/s air flow. These parameters do not characterize the package alone but rather the package mounted on the JEDEC-defined PCB. Different applications conditions (PCB stack-up and size, air flow speed, etc.) may result in different thermal characteristics.