67.8 Power Consumption in Active Mode

Table 67-54 provides the processor power consumption in the following conditions:

f_{CPU_CLK} = from 200 MHz to 800 MHz
f_MCK = 100 MHz to 266 MHz
L1 caches enabled
The Arm926EJ-S core executes a Coremark benchmark from the (internal) SRAM0
Code compiled with speed optimization
Peripheral clocks disabled
Current measured as per Figure 67-36

Figure 67-36. Current Measurement on VDDCORE

Table 67-54. Processor Power Consumption Running a Coremark Benchmark from SRAM0
f_{CPU_CLK}/f_MCK	I_DDCORE vs T_A
f_{CPU_CLK}/f_MCK	-40°C	0°C	25°C	50°C	85°C	105°C
200 MHz/100 MHz	50	54	54	62	82	95
400 MHz/200 MHz	85	89	89	97	116	130
600 MHz/200 MHz	105	110	110	120	138	152
800 MHz/266 MHz	135	140	140	150	167	182

Figure 67-37. Processor Current Consumption Running a Coremark Benchmark from SRAM0

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