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Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Arm® Arm926EJ-S™ Processor-Based MPU, 800 MHz, MIPI DSI or CSI-2, LVDS, RGB, 2D Graphics, Gigabit Ethernet with TSN, CAN-FD, Octal/Quad SPI, Crypto, PUF
Product Pages
SAM9X70 SAM9X72 SAM9X75
  1. Home
  2. 54 Physical Unclonable Functions (PUF)
  3. 54.5 Functional Description
  4. 54.5.5 PUF Controller Operations
  5. 54.5.5.11 Generate Random Operation
  • Introduction
  • Features
  • 1 Configuration Summary
  • 2 Block Diagram
  • 3 Signal Description
  • 4 Microchip Recommended Power Management Solutions
  • 5 Safety and Security Features
  • 6 Package and Pinout
  • 7 Peripherals
  • 8 Arm926EJ-S Processor
  • 9 Debug and Test
  • 10 Bus Matrix (MATRIX)
  • 11 DMA Controller (XDMAC)
  • 12 Boot Strategies
  • 13 SYSTEM CONTROLLER SUBSYSTEM
  • 14 System Controller Write Protection (SYSCWP)
  • 15 Advanced Interrupt Controller (AIC)
  • 16 Boot Sequence Controller (BSC)
  • 17 General Purpose Backup Registers (GPBR)
  • 18 Watchdog Timer (WDT)
  • 19 Reset Controller (RSTC)
  • 20 Real-Time Timer (RTT)
  • 21 Real-time Clock (RTC)
  • 22 Shutdown Controller (SHDWC)
  • 23 Periodic Interval Timer (PIT)
  • 24 64-bit Periodic Interval Timer (PIT64B)
  • 25 Debug Unit (DBGU)
  • 26 Special Function Registers (SFR)
  • 27 Slow Clock Controller (SCKC)
  • 28 Clock Generator
  • 29 Power Management Controller (PMC)
  • 30 Parallel Input/Output Controller (PIO)
  • 31 MEMORIES
  • 32 Static Memory Controller (SMC)
  • 33 Programmable Multibit Error Correction Code Controller (PMECC)
  • 34 Programmable Multibit ECC Error Location Controller (PMERRLOC)
  • 35 DDR-SDRAM Controller (MPDDRC)
  • 36 OTP Memory Controller (OTPC)
  • 37 IMAGE SUBSYSTEM
  • 38 LCD Controller (LCDC)
  • 39 Low Voltage Differential Signaling Controller (LVDSC)
  • 40 2D Graphics Engine (GFX2D)
  • 41 Display Serial Interface (DSI)
  • 42 Camera Serial Interface (CSI)
  • 43 CSI-2 Demultiplexer Controller (CSI2DC)
  • 44 Image Sensor Controller (ISC)
  • 45 AUDIO SUBSYSTEM
  • 46 Audio Class D Amplifier (CLASSD)
  • 47 Inter-IC Sound Multi-Channel Controller (I2SMCC)
  • 48 Synchronous Serial Controller (SSC)
  • 49 CRYPTOGRAPHY SUBSYSTEM
  • 50 Advanced Encryption Standard (AES)
  • 51 Secure Hash Algorithm (SHA)
  • 52 Triple Data Encryption Standard (TDES)
  • 53 True Random Number Generator (TRNG)
  • 54 Physical Unclonable Functions (PUF)
    • 54.1 Description
    • 54.2 Embedded Characteristics
    • 54.3 Block Diagram
    • 54.4 Product Dependencies
    • 54.5 Functional Description
      • 54.5.1 PUF Introduction
      • 54.5.2 PUF Operations
      • 54.5.3 Security Strength Versus Key Length
      • 54.5.4 PUF Controller States
      • 54.5.5 PUF Controller Operations
        • 54.5.5.1 Introduction
        • 54.5.5.2 Initialization Operation
        • 54.5.5.3 Enroll Operation
        • 54.5.5.4 Start Operation
        • 54.5.5.5 Reconstruct Operation
        • 54.5.5.6 Stop Operation
        • 54.5.5.7 Get Key Operation
        • 54.5.5.8 Wrap Generated Random Operation
        • 54.5.5.9 Wrap Operation
        • 54.5.5.10 Unwrap Operation
        • 54.5.5.11 Generate Random Operation
        • 54.5.5.12 Reseed Operation
        • 54.5.5.13 Test Memory Operation
        • 54.5.5.14 Test PUF Operation
        • 54.5.5.15 Zeroize Operation
      • 54.5.6 PUF Data Formats
      • 54.5.7 PUF Operation Restrictions
      • 54.5.8 PUF Error Handling
      • 54.5.9 PUF Diagnostics
      • 54.5.10 PUF Built-in Tests
      • 54.5.11 PUF Deterministic Random Number Generator (DRNG)
    • 54.6 Register Summary
  • 55 CONNECTIVITY SUBSYSTEM
  • 56 Ethernet MAC (GMAC)
  • 57 Flexible Serial Communication Controller (FLEXCOM)
  • 58 Quad Serial Peripheral Interface (QSPI)
  • 59 Secure Digital MultiMedia Card Controller (SDMMC)
  • 60 Controller Area Network (MCAN)
  • 61 Timer Counter (TC)
  • 62 Pulse Width Modulation Controller (PWM)
  • 63 USB SUBSYSTEM
  • 64 USB Device High Speed Port (UDPHS)
  • 65 USB Host High Speed Port (UHPHS)
  • 66 Analog-to-Digital Controller (ADC)
  • 67 Electrical Characteristics
  • 68 Mechanical Characteristics
  • 69 Marking
  • 70 Ordering Information
  • 71 Revision History
  • Microchip Information

54.5.5.11 Generate Random Operation

The Generate Random operation outputs the requested amount of random data as specified in a provided context. The context is defined in Context Specification for Generate Random Operation.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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