58.6.2 Updating the QSPI Configuration

At any time, the QSPI Controller core configuration can be updated by writing the QSPI_CR.UPDCFG bit to ‘1’. Note that QSPI_SR.SYNCBSY must be ‘0’ before writing QSPI_CR.UPDCFG.

The configuration registers that require synchronization (writing QSPI_CR.UPDCFG to ‘1’) with the QSPI Controller core are:

  • QSPI_MR
  • QSPI_SCR
  • QSPI_IAR
  • QSPI_WICR
  • QSPI_IFR
  • QSPI_RICR
  • QSPI_SMR
  • QSPI_SKR
  • QSPI_REFRESH
  • QSPI_WRACNT
  • QSPI_PCALCFG