58.6.4 Transfer Delays

The figures below show several consecutive transfers while the chip select is active. Three delays can be programmed to modify the transfer waveforms:

• The delay between the deactivation and the activation of QCS, programmed by writing QSPI_MR.DLYCS—to adjust the minimum time of QCS at high level.
• The delay before QSCK, programmed by writing QSPI_SR.DLYBS—to start delaying QSCK after the chip select has been asserted.
• The delay between consecutive transfers, programmed by writing QSPI_MR.DLYBCT.
  • If QSPI_MR.SMM = 0, to insert a delay between two consecutive transfers.
  • If QSPI_MR.SMM = 1, to insert a delay between the last QSCK pulse and the QCS rise.

These delays allow the QSPI to be adapted to the interfaced peripherals and their speed and bus release time.