35.5.4.3 Change Frequency During Self-Refresh Mode with DDR2-SDRAM and DDR3-SDRAM Devices

To change frequency, Self-refresh mode must be activated. This is done by configuring the Low-power Command bit (LPCB) to 1 and writing a ‘1’ to the Change Frequency Command bit (CHG_FR) in the Low-power register (MPDDRC_LPR).

Once the DDR-SDRAM device is in Self-refresh mode, the user must make sure there is no access in progress. Then, the user can change the clock frequency. The device input clock frequency changes only within minimum and maximum operating frequencies as specified by the DDR2-SDRAM and DDR3-SDRAM providers. The MPDDRC_RTR (COUNT), MPDDRC_CR (CAS, etc.), MPDDRC_TPR0 (TRC, TRP, TRAS, etc.), MPDDRC_TPR1 (TRFC, TXSNR, TXSRD, TXP) and MPDDRC_TPR2 (TRTP, TFAW, etc.) registers can be updated according to the new clock frequency. Once the input clock frequency is changed, new stable clocks must be provided to the device before exiting from Self-refresh mode.

To exit from Self-refresh mode, the DDR-SDRAM device must be selected. The MPDDRC provides a sequence of commands and exits Self-refresh mode.

During a change frequency procedure, MPDDRC_LPR.CHG_FR is set to 0 automatically.

Before changing frequency, make sure the processor clock (PCK) value is twice the system bus clock (MCK) value.