35.5.4.1 Self-Refresh Mode
This mode is activated by configuring the Low-power Command bit (LPCB) to 1 in the MPDDRC Low-Power Register (MPDDRC_LPR).
Self-refresh mode is used in Power-down mode, that is, when no access to the DDR-SDRAM device is possible. In this case, power consumption is very low. In Self-refresh mode, the DDR-SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. During the self-refresh period, CKE is driven low. As soon as the DDR-SDRAM device is selected, the MPDDRC provides a sequence of commands and exits Self-refresh mode.
The MPDDRC re-enables Self-refresh mode as soon as the DDR-SDRAM device is not selected. It is possible to define when Self-refresh mode is to be enabled by configuring the TIMEOUT field in the MPDDRC_LPR:
0: Self-refresh mode is enabled as soon as the DDR-SDRAM device is not selected.
1: Self-refresh mode is enabled 64 clock cycles after completion of the last access.
2: Self-refresh mode is enabled 128 clock cycles after completion of the last access.
Disabled banks are not refreshed in Self-refresh mode. This feature permits to reduce the self-refresh current.
The DDR2-SDRAM must remain in Self-refresh mode during the minimum of tCKE periods (refer to the memory device data sheet), and may remain in Self-refresh mode for an indefinite period.
The DDR3-SDRAM must remain in Self-refresh mode for the minimum of tCKESR periods (refer to the memory device data sheet) and may remain in Self-refresh mode for an indefinite period.