38.4 I/O Lines Description

Table 38-1. I/O Lines Description
Name Description Type
LCDC_PWM Contrast control signal, using Pulse Width Modulation Output
LCDC_HSYNC Horizontal Synchronization Pulse Output
LCDC_VSYNC Vertical Synchronization Pulse Output
LCDC_DAT[23:0] LCD 24-bit data bus Output
LCDC_DEN Data Enable Output
LCDC_DISP Display Enable signal Output
LCDC_PCK Pixel Clock Output
MIPI_CLKP MIPI DPHY differential output clock lane Input/Output
MIPI_CLKN
MIPI_DP0 MIPI DPHY differential output data lane 0 Input/Output
MIPI_DN0
MIPI_DP1 MIPI DPHY differential output data lane 1 Input/Output
MIPI_DN1
MIPI_DP2 MIPI DPHY differential output data lane 2 Input/Output
MIPI_DN2
MIPI_DP3 MIPI DPHY differential output data lane 3 Input/Output
MIPI_DN3
MIPI_REXT Calibration reference resistor Input/Output
LVDS_CLK1P Differential LVDS clock line transceiver output Output
LVDS_CLK1M
LVDS_A0P Differential LVDS data 0 line transceiver output Output
LVDS_A0M
LVDS_A1P Differential LVDS data 1 line transceiver output Output
LVDS_A1M
LVDS_A2P Differential LVDS data 2 line transceiver output Output
LVDS_A2M
LVDS_A3P Differential LVDS data 3 line transceiver output Output
LVDS_A3M