38.6 Functional Description

The LCDC module integrates the following digital blocks:

• DMA Engine—this block performs data prefetch and requests access to the system bus interface.
• Input Layer FIFO—stores the stream of pixels
• Color Look-up Table (CLUT)—these 256 RAM-based look-up table entries are selected when the color depth is set to 1, 2, 4 or 8 bpp.
• Color Space Conversion (CSC)—changes the color space from YCbCr to RGB
• Two Dimension Scaler (2DSC)—resizes the image
• Global Alpha Blender (GAB)—performs programmable 256-level alpha blending
• Output FIFO—stores the blended pixel prior to display
• LCD Timing Engine—provides a fully programmable HSYNC-VSYNC interface

The DMA controller reads the image through the system bus host interface. The LCDC engine formats the display data, then the GAB performs alpha blending if required, and writes the final pixel into the output FIFO. The programmable timing engine drives a valid pixel onto the LCD_DAT_EVEN[23:0] display bus .