46.6.1.1 Clock Configuration
The interpolator accepts input sampling frequencies (fs) and the input DSP clock (DSPCLK) that can be configured in the CLASSD Interpolator Mode Register. GCLK must be configured in the PMC according to the desired DSPCLK so that DSPCLK = GCLK / 8.
The following table provides authorized DSPCLK / fs ratios and associated filter types.
| fs | DSPCLK | |
|---|---|---|
| 12.288 MHz | 11.2896 MHz | |
| 8 kHz | 2 | – |
| 16 kHz | 2 | – |
| 32 kHz | 2 | – |
| 48 kHz | 1 | – |
| 96 kHz | 3 | – |
| 22.05 kHz | – | 1 |
| 44.1 kHz | – | 1 |
| 88.2 kHz | – | 3 |
Note: Each dash (–) indicates a configuration
that is not authorized and that raises the CFGERR flag in CLASSD_INTSR.