41.6.3.1 Initialization
The Input Video interface captures the data and control signals from the LCD Controller (LCDC) and conveys them to the FIFO interfaces that transmit them to the DSI link. Two different streams of data are presented at the interface; video control signals and pixel data.
Depending on the interface color coding, the pixel data is disposed differently throughout the bus. Interface pixel color coding is shown in the table below:
| Order | 16-bit Config 1 | 16-bit Config 2 | 16-bit Config 3 | 18-bit Config 1 | 18-bit Config 2 | 24-bit | DSC24 |
|---|---|---|---|---|---|---|---|
| D23 | – | – | – | – | – | R[7] | Byte1[7] |
| D22 | – | – | – | – | – | R[6] | Byte1[6] |
| D21 | – | – | R[4] | – | R[5] | R[5] | Byte1[5] |
| D20 | – | R[4] | R[3] | – | R[4] | R[4] | Byte1[4] |
| D19 | – | R[3] | R[2] | – | R[3] | R[3] | Byte1[3] |
| D18 | – | R[2] | R[1] | – | R[2] | R[2] | Byte1[2] |
| D17 | – | R[1] | R[0] | R[5] | R[1] | R[1] | Byte1[1] |
| D16 | – | R[0] | – | R[4] | R[0] | R[0] | Byte1[0] |
| D15 | R[4] | – | – | R[3] | – | G[7] | Byte2[7] |
| D14 | R[3] | – | – | R[2] | – | G[6] | Byte2[6] |
| D13 | R[2] | G[5] | G[5] | R[1] | G[5] | G[5] | Byte2[5] |
| D12 | R[1] | G[4] | G[4] | R[0] | G[4] | G[4] | Byte2[4] |
| D11 | R[0] | G[3] | G[3] | G[5] | G[3] | G[3] | Byte2[3] |
| D10 | G[5] | G[2] | G[2] | G[4] | G[2] | G[2] | Byte2[2] |
| D9 | G[4] | G[1] | G[1] | G[3] | G[1] | G[1] | Byte2[1] |
| D8 | G[3] | G[0] | G[0] | G[2] | G[0] | G[0] | Byte2[0] |
| D7 | G[2] | – | – | G[1] | – | B[7] | Byte3[7] |
| D6 | G[1] | – | – | G[0] | – | B[6] | Byte3[6] |
| D5 | G[0] | – | B[4] | B[5] | B[5] | B[5] | Byte3[5] |
| D4 | B[4] | B[4] | B[3] | B[4] | B[4] | B[4] | Byte3[4] |
| D3 | B[3] | B[3] | B[2] | B[3] | B[3] | B[3] | Byte3[3] |
| D2 | B[2] | B[2] | B[1] | B[2] | B[2] | B[2] | Byte3[2] |
| D1 | B[1] | B[1] | B[0] | B[1] | B[1] | B[1] | Byte3[1] |
| D0 | B[0] | B[0] | – | B[0] | B[0] | B[0] | Byte3[0] |
These configuration options are as follows:
- Polarity control: All the control signals are programmable to change the polarity depending on the LCDC configuration.
- After the controller reset, the input video interface waits for the first VSYNC active transition to start signal sampling, including pixel data, thus avoiding starting the transmission of the image data in the middle of a frame.
- If the interface pixel color coding is 18 bits and the 18-bit loosely packed stream is disabled, the number of pixels programmed in the field VID_PKT_SIZE in the Video Mode Packet Size Configuration register (DSI_VID_PKT_SIZE) must be a multiple of four. This means that in this mode, the two LSBs in the configuration are always inferred as zero. The specification states that in this mode, the pixel line size should be a multiple of four.
- To avoid FIFO underflows and overflows, the configured number of pixels is assumed to be received at all times. A set of bits in the DSI_VID_PKT_STATUS register report the status of the FIFOs and internal buffers associated with the input video interface support.
- To keep the memory organized with respect to the packet scheduling, the number of pixels per packet parameter is used to separate the memory space of different video packets.
For Shutdown and Color mode signal transmission, the input video signaling must be active. Because of such constraints and for commands to be correctly transmitted, the first VSYNC active pulse should occur for command sampling and transmission. When shutting down the display, the input video must remain active for one frame after the command has been issued. This ensures that the commands are correctly transmitted before disabling the video generation at the input video interface.