41.6.2.3 D-PHY PLL Control Operation

The D-PHY includes a fully programmable PLL, enabling a flexible lane bit rate value. The generated clock frequency (fout) is a function of the input reference frequency and of the multiplication and division ratios. It can be determined as follows:

f out = M N ⋅ f ref

Where:

  • M = feedback multiplication ratio
  • N = input frequency division ratio
  • fref = frequency of the main crystal oscillator. fref = 24 MHz.

Note that the following limit applies:

40 MHz ≥ f ref N ≥ 5 MHz

The PLL output clock (with frequency fout) is the full-rate clock used for bit serialization. A 1000 Mbps bit rate on the data lanes assumes PLL output frequency to be equal to 1000 MHz.

The D-PHY also generates the lanebyteclk clock signal with a frequency of fout/8.

The PLL output frequency ranges are selected from the following table:

Table 41-4. PLL Output Frequency Ranges
Ranges (Mbps) PLL Output Frequency Range (MHz)
000 80-200
001 200-300
010 300-500
011 500-700
100 700-900
101 900-1000

Some combinations of N and M are not allowed, since they violate the limits of operation of the PLL output frequency or the minimum allowed comparison frequency. Due to the use of a “by 2 pre-scaler” the range of the feedback multiplication value M is limited to even division numbers.

To ensure proper operation of the PLL, the loop bandwidth should be configured depending on the selected frequency. The control over the Charge Pump (CP) current (ICPCTRL[3:0]), the Low-Pass Filter (LPF) characteristics (LPFCTRL[5:0]), and VCO control signals (VCORANGE and VCOCAP) is granted. The table below presents the correspondence.

Table 41-5. PLL CP and LPF Control Fields
PLL Output Frequency Range (MHz) VCORANGE ICPCTRL LPFCTRL VCOCAP
80-110 000 0100 010000 00
110-150 1000 001000 00
150-200 1100 001000 00
200-250 001 1100 001000 00
250-300 0010 001000 00
300-400 010 0101 001000 00
400-500 0101 000001 00
500-600 011 0110 010000 00
600-700 0110 000100 00
700-900 100 0110 000100 00
900-1000 101 0111 010000 00

To configure D-PHY PLL, follow the steps below in conjunction with the procedure in General D-PHY Control Operation:

  1. Configure the VCO parameters with the test code 0x10 and data as follows:
    • Bit 7:

      0: VCO range is programmed with the default values for the corresponding hsfreqrange

      1: VCO range is programmed with bits 5:3

    • Bit 6: Reserved
    • Bits 5:3: VCO range control (vcorange)
    • Bits 2:1: VCO internal capacitance control (vcocap)

      00: Default capacitance

      01: Low capacitance (four times lower than the default value)

      10: High capacitance (double the default value)

      11: Not allowed

    • Bit 0: Reserved
  2. Configure PLL Control with test code 0x11 and data icpctrl.
  3. Configure PLL Control with test code 0x12 and data as follows:
    • Bit 7: Bypass CP default values

      0: vcocap is programmed with the default values for the corresponding hsfreqrange

      1: vcocap is programmed with bits 3:0 using test code 0x11

    • Bit 6: Bypass LPF default values

      0: LPF is programmed with the default values for the corresponding hsfreqrange

      1: LPF is programmed with bits 5:0

    • Bit 5:0: Loop filter control (lpfctrl)

      000000: Loop Filter resistor is 18kΩ

      000001: Loop Filter resistor is 15.6kΩ

      000010: Loop Filter resistor is 15kΩ

      000100: Loop Filter resistor is 14.4kΩ

      001000: Loop Filter resistor is 12.8kΩ

      010000: Loop Filter resistor is 11.4kΩ

      100000: Loop Filter resistor is 10.5kΩ

  4. Enable N and M values with test code 0x19 and data as follows:
    • Bits 7:6: Reserved
    • Bit 5: Bypass the PLL loop divider default values

      0: PLL loop divider is programmed with the default values for the corresponding hsfreqrange

      1: PLL loop divider is programmed using the test code 8'h18 (PLL Loop Divider Ratio)

    • Bit 4: Bypass PLL input divider default values

      0: PLL input divider is programmed with the default values for the corresponding hsfreqrange

      1: PLL input divider is programmed using test code 8'h17 (PLL Input Divider Ratio)

    • Bits 3:0: Reserved
  5. Configure PLL Input Divider Ratio (N) with test code 0x17 and data assigned to N-1
  6. Configure PLL Loop Divider Ratio (M) with test code 0x18 and data as follows:

    For m = M-1:

    • Data bit 7: Bit Field Selector
      • When data bit 7 is 0, LSBs are accessed:
        • data bits 6:5: Reserved
        • data bits 4:0: m[4:0]
      • When data bit 7 is 1 : MSBs are accessed:
        • data bits 6:4: Reserved
        • data bits 3:0: m[8:5]