2.3 Electrical Parameters and Values

Table 2-1. SY75712 Current ConsumptionV_DD = 1.8V ±10%, V_DD = 1.5V ±10%, V_DD = 1.2V ±10%, T_A = –40°C to +105°C
Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
V_DD Supply Current	I_{DD_1.8V}	—	6.5	7.5	mA	Note 1
	I_{DD_1.5V}	—	5.3	6.1
	I_{DD_1.2V}	—	4.1	4.7
Note: Tested with 25 MHz clock with outputs driving 4” long trace with 50Ω characteristic impedance, terminated with 2 pF capacitors to ground.

Table 2-2. SY75714 Current ConsumptionV_DD = 1.8V ±10%, V_DD = 1.5V ±10%, V_DD = 1.2V ±10%, T_A = –40°C to +105°C
Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
V_DD Supply Current	I_{DD_1.8V}	—	9.8	11.3	mA	Note 1
	I_{DD_1.5V}	—	8.0	9.2
	I_{DD_1.2V}	—	6.3	7.3
Note: Tested with 25 MHz clock with outputs driving 4” long trace with 50Ω characteristic impedance, terminated with 2 pF capacitors to ground.

Table 2-3. Input Electrical CharacteristicsV_DD = 1.8V ±10%, V_DD = 1.5V ±10%, V_DD = 1.2V ±10%, T_A = –40°C to +105°C
Parameter	Symbol	Min.	Typ.	Max.	Units	Condition
Input High Voltage	V_IH	0.7 × V_DD	—	—	V	—
Input Low Voltage	V_IL	—	—	0.3 × V_DD	V	—
Input Leakage Current	I_{IL_IN}	–5	—	50	µA	V_IN = V_INMAX, V_IN = GND
Input Capacitance	C_IN	—	—	5	pF	—
Input Leakage Current for OExb Inputs (includes current due to pull-down resistors)	I_{IL_OE}	–5	—	50	µA	V_IN = V_DD,V_IN = GND
Maximum Input Voltage	V_INMAX	—	—	V_DD + 0.4	V	—
Minimum Input Voltage	V_INMIN	–0.3	—	—	V	—
Input Frequency	f_IN	0	—	250	MHz	—
Input Pulse Width	t_PW	2	—	—	ns	—
Input Rise/Fall Time (20% to 80%)	t_r/t_f	—	0.6	10	ns	—

Table 2-4. Output Electrical CharacteristicsV_DD = 1.8V ±10%, V_DD = 1.5V ±10%, V_DD = 1.2V ±10%, T_A = –40°C to +105°C, see Note 1
Parameter	Symbol	Min.	Typ.	Max.	Units	Conditions
Output Rise Time (20% to 80%)	t_r	—	350	580	ps	Note 1
Output Edge Fall Time (80% to 20%)	t_f	—	350	580	ps	Note 1
Output High Voltage	V_OH	0.8 × V_DD	—	—	V	I_OUT = 3 mA
Output Low Voltage	V_OL	—	—	0.2 × V_DD	V	I_OUT = –3 mA
Output Duty Cycle (when input has 50% duty cycle)	DC	45	50	55	%	f_OUT = 156.25 MHz
Output Frequency	f_MAX	0	—	250	MHz	—
Output-to-Output Skew	t_OOSK	—	38	50	ps	—
Device-to-Device Skew	t_DDSK	—	—	550	ps	—
Input-to-Output Delay	t_{IOD_CMOS_IN}	1.1	1.5	2.1	ns	—
Output Enable Time	t_EN	3	—	5	Clock cycles	—
Output Disable Time	t_DIS	3	—	5	Clock cycles	—
Output Impedance	O_IMP	40	50	60	Ω	Note 2
Notes: Bench tested with 100 MHz clock with outputs driving 4” long trace with 50Ω characteristic impedance, terminated with 2 pF capacitors to ground. 50Ω output impedance is with 1.2V V_DD. When output is powered with 1.8V V_DD, the output impedance will be slightly lower (approximately 40Ω).

Table 2-5. SY75712/14 Jitter and Phase Noise
Parameter	Symbol	Min.	Typ.	Max.	Units	Conditions
V_DD = 1.8V ±10%, T_A = –40°C to +105°C, see Note 1
Additive RMS Jitter in 1 MHz to 5 MHz Band	t_{j_1M_5M}	—	15.3	26.5	fs_RMS	25 MHz clock
Additive RMS Jitter in 1 MHz to 20 MHz Band	t_{j_1M_20M}	—	16.0	25.2	fs_RMS	100 MHz clock
Additive RMS Jitter in 1 MHz to 20 MHz Band	t_{j_1M_20M}	—	15.8	24.7	fs_RMS	156.25 MHz clock
Additive RMS Jitter in 12 kHz to 5 MHz Band	t_{j_12k_5M}	—	19.7	34.4	fs_RMS	25 MHz clock
Additive RMS Jitter in 12 kHz to 20 MHz Band	t_{j_12k_20M}	—	16.9	26.3	fs_RMS	100 MHz clock
Additive RMS Jitter in 12 kHz to 20 MHz Band	t_{j_12k_20M}	—	16.9	26.1	fs_RMS	156.25 MHz clock
Noise Floor	N_F	—	–175.2	—	dBc/Hz	25 MHz clock
		—	–172.8	—	dBc/Hz	100 MHz clock
		—	–169.7	—	dBc/Hz	156.25 MHz clock
V_DD = 1.2V ±10%, T_A = –40°C to +105°C, see Note 1
Additive RMS Jitter in 1 MHz to 5 MHz Band	t_{j_1M_5M}	—	35.1	56.8	fs_RMS	25 MHz clock
Additive RMS Jitter in 1 MHz to 20 MHz Band	t_{j_1M_20M}	—	33.7	53.9	fs_RMS	100 MHz clock
Additive RMS Jitter in 1 MHz to 20 MHz Band	t_{j_1M_20M}	—	32.0	48.7	fs_RMS	156.25 MHz clock
Additive RMS Jitter in 12 kHz to 5 MHz Band	t_{j_12k_5M}	—	42.2	66.7	fs_RMS	25 MHz clock
Additive RMS Jitter in 12 kHz to 20 MHz Band	t_{j_12k_20M}	—	36.3	57.1	fs_RMS	100 MHz clock
Additive RMS Jitter in 12 kHz to 20 MHz Band	t_{j_12k_20M}	—	35.9	53.5	fs_RMS	156.25 MHz clock
Noise Floor	N_F	—	–171.9	—	dBc/Hz	25 MHz clock
		—	–168.8	—	dBc/Hz	100 MHz clock
		—	–165.2	—	dBc/Hz	156.25 MHz clock
Note: Tested with input fed with low jitter clock from R&S SMA100B function generator and with outputs driving R&S FSWP8 Phase Noise Analyzer via SMA cable.