4.4 Reset (RST)
CryptoMemory® provides an ISO 7816-3 compliant asynchronous Answer-to-Reset (ATR) sequence. When the reset sequence is activated, the device will output the data programmed into the 64-bit ATR register. When RST is low, all internal logic, access rights, and write cycles are in reset, except the Asynchronous mode activation flag. A weak internal pull-up on the RST input pad allows the device to be used in Synchronous mode without bonding RST. For synchronous-only smart card applications, an external pull-up on RST is recommended to ensure synchronous operation under any system timings or conditions. CryptoMemory does not support a synchronous ATR sequence. The RST input is not available in the plastic package options for CryptoMemory.
