36.4 Supply Voltage

Table 36-3. Supply Voltage
Symbol		Min.	Typ. ✝	Max.	Units	Conditions
Supply Voltage⁽¹⁾
V_DD		1.8	—	5.5	V
Slew Rate		—	—	1.5	V/µs	1.8V ≤ V_DD ≤ 5.5V
V_DD Range for Operating the USB Voltage Regulator
V_DDU		3.9	—	V_{DD_MAX}	V	V_DDU = V_DD
Supply Voltage for USB Transceiver
V_USB			3.3		V
Quiescent Input Current of the USB Regulator
I_Q			180		µA	USB regulator without load
Input Leakage on the Regulator Output (VUSB Pin)
I_VUSB	Sink current	—	-10	—	mA	`SYSCFG1.USBSINK = 0x01` This is for the fault condition when the USB regulator output voltage is driven externally at V_{USB_SINK} or above
I_VUSB	Source current	—	30	—	mA	3.9 ≤ V_DDU ≤ V_{DD_MAX}
Sink Function Trigger Point
V_{USB_SINK}			6		%	Percent above V_USB
RAM Data Retention⁽²⁾
V_DR		1.7	—	—	V	Device in Power-Down mode
Power-on Reset Release Voltage⁽⁴⁾
V_POR		—	1.6	—	V	BOD disabled⁽³⁾
t_POR		—	1	—	μs	BOD disabled⁽³⁾
Power-on Reset Re-Arm Voltage⁽⁴⁾
V_PORR		—	1.25	—	V	BOD disabled⁽³⁾
t_PORR		—	2.7	—	μs	BOD disabled⁽³⁾
V_DD Rise Rate to Ensure Internal Power-on Reset Signal⁽⁴⁾
S_VDD		0.05	—	—	V/ms	BOD disabled⁽³⁾
✝ Data in the “Typ.” column is at T_A = 25°C and V_DD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested. Note: During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. If the supply voltage V_DD is below V_BOD for BODLEVEL0, the erase attempt will fail. This is the limit to which V_DD can be lowered in sleep mode without losing RAM data. Refer to section RSTCTRL for BOD trip point information. Refer to the figure POR and PORR with Slow Rising V_DD.

Figure 36-1. POR and PORR with Slow Rising V_DD

Note:

When POR is low, the device is held in Reset