36.4 Supply Voltage

Table 36-3. Supply Voltage
Symbol Min. Typ. ✝ Max. Units Conditions
Supply Voltage(1)
VDD

1.8

 —

5.5

V
Slew Rate — — 1.5 V/µs 1.8V ≤ VDD ≤ 5.5V
VDD Range for Operating the USB Voltage Regulator
VDDU

3.9

 —

VDD_MAX

V

 VDDU = VDD
Supply Voltage for USB Transceiver
VUSB 3.3

V
Quiescent Input Current of the USB Regulator
IQ 180 µA USB regulator without load
Input Leakage on the Regulator Output (VUSB Pin)
IVUSB Sink current — -10 — mA SYSCFG1.USBSINK = 0x01

This is for the fault condition when the USB regulator output voltage is driven externally at VUSB_SINK or above
Source current — 30 — mA 3.9 ≤ VDDU ≤ VDD_MAX
Sink Function Trigger Point
VUSB_SINK 6 % Percent above VUSB
RAM Data Retention(2)
VDR

1.7

—

—

V

 Device in Power-Down mode
Power-on Reset Release Voltage(4)
VPOR

—

1.6

—

V

 BOD disabled(3)
tPOR

—

1

—

μs

 BOD disabled(3)
Power-on Reset Re-Arm Voltage(4)
VPORR

—

 1.25

—

V

 BOD disabled(3)
tPORR

—

2.7

—

μs

 BOD disabled(3)
VDD Rise Rate to Ensure Internal Power-on Reset Signal(4)
SVDD 0.05

—

—

 V/ms BOD disabled(3)

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are for design guidance only and are not tested.

Note:
  1. During Chip Erase, the Brown-out Detector (BOD) configured with BODLEVEL0 is forced ON. If the supply voltage VDD is below VBOD for BODLEVEL0, the erase attempt will fail.
  2. This is the limit to which VDD can be lowered in sleep mode without losing RAM data.
  3. Refer to section RSTCTRL for BOD trip point information.
  4. Refer to the figure POR and PORR with Slow Rising VDD.
Figure 36-1. POR and PORR with Slow Rising VDD
Note:
  • When POR is low, the device is held in Reset