36.15 TWI

Figure 36-7. TWI - Timing Requirements
Table 36-21. TWI - Timing Characteristics
Symbol Description Min. Typ. Max. Unit Condition
fSCL SCL clock frequency 0 — 1000 kHz Max. frequency requires system clock at 10 MHz
0 — 400 kHz For VDD < 2.2V
VIH Input high voltage 0.7×VDD — — V
VIL Input low voltage — — 0.3×VDD V
VHYS Hysteresis of Schmitt Trigger inputs 0.1×VDD 0.4×VDD V
VOL Output low voltage — — 0.2xVDD V Iload = 20 mA, Fast mode+
— — 0.4V Iload = 3 mA, Normal mode, VDD > 2V
— — 0.2×VDD Iload = 3 mA, Normal mode, VDD ≤ 2V
IOL Low level output current 3 — — mA fSCL ≤ 400 kHz, VOL = 0.4V
20 — — fSCL ≤ 1 MHz, VOL = 0.4V
CB Capacitive load for each bus line — — 400 pF fSCL ≤ 100 kHz
— — 400 fSCL ≤ 400 kHz
— — 550 fSCL ≤1 MHz
tR Rise time for both SDA and SCL — — 1000 ns fSCL ≤ 100 kHz
20 — 300 fSCL ≤ 400 kHz
— — 120 fSCL ≤ 1 MHz
tOF Output fall time from VIHmin to VILmax — — 250 ns

fSCL ≤ 100 kHz

10 pF < CB < 400 pF
20×(VDD/5.5V) — 250

fSCL ≤ 400 kHz

10 pF < CB < 400 pF
20×(VDD/5.5V) — 120

fSCL ≤ 1 MHz

10 pF < CB < 400 pF
tSP Spikes suppressed by the input filter 0 — 50 ns
IL Input current for each I/O pin — — 1 µA 0.1×VDD < VI < 0.9×VDD
CI Capacitance for each I/O pin — — 10 pF
RP Value of pull-up resistor (VDD-VOL(max)) /IOL — 1000 ns/(0.8473×CB) Ω fSCL ≤ 100 kHz
— — 300 ns/(0.8473×CB) fSCL ≤ 400 kHz
— — 120 ns/(0.8473×CB) fSCL ≤ 1 MHz
tHD_STA Hold time (repeated) Start condition 4.0 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
— 2.1 — TSCL Start
— 3.1 — Repeated Start
TLOW Low period of SCL Clock 4.7 — — µs fSCL ≤ 100 kHz
1.3 — — fSCL ≤ 400 kHz
0.5 — — fSCL ≤ 1 MHz
THIGH High period of SCL Clock 4.0 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
tSU_STA Setup time for a repeated Start condition 4.7 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
— 3 — TSCL
tHD_DAT Data hold time — 0 — ns SDAHOLD[1:0] = 0x0
30 — 300 SDAHOLD[1:0] = 0x1
120 — 420 SDAHOLD[1:0] = 0x2
300 — 900 SDAHOLD[1:0] = 0x3
tSU_DAT Data setup time 250 — — ns fSCL ≤ 100 kHz
100 — — fSCL ≤ 400 kHz
50 — — fSCL ≤ 1 MHz
tSU_STO Setup time for Stop condition 4 — — µs fSCL ≤ 100 kHz
0.6 — — fSCL ≤ 400 kHz
0.26 — — fSCL ≤ 1 MHz
— 2 — TSCL
tBUF Bus free time between a Stop and Start condition 4.7 — — µs fSCL ≤ 100 kHz
1.3 — — fSCL ≤ 400 kHz
0.5 — — fSCL ≤ 1 MHz
— 2 — TSCL
Note: I2C Fm+ is supported only for above 2.7V.