6.8.4.5 System Configuration 0
| Name: | SYSCFG0 |
| Offset: | 0x05 |
| Reset: | - |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCBOOTDIS | CRCAPPDIS | RESERVED[1:0] | RSTPINCFG[1:0] | RESERVED | EESAVE | ||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | |
Bit 7 – CRCBOOTDIS CRC of Boot Section in Reset Disable
| Value | Description |
|---|---|
| 0 | Boot section undergoing a CRC before Reset releases |
| 1 | No CRC of the boot section before Reset releases |
Bit 6 – CRCAPPDIS CRC of Application Code Section in Reset Disable
| Value | Description |
|---|---|
| 0 | Application code section undergoing a CRC before Reset releases |
| 1 | No CRC of the application code section before Reset releases |
Bits 5:4 – RESERVED[1:0]
Bits 3:2 – RSTPINCFG[1:0] Reset Pin Configuration
| Value | Description |
|---|---|
| 0x0 | GPIO |
| 0x1 | RESET |
| 0x2 | UPDI |
| 0x3 |
For 24-pin device: UPDI, with external Reset on alternate location. Reserved for lower pin-counts. |
Bit 1 – RESERVED
Bit 0 – EESAVE EEPROM Save during chip erase
Note: If the device is locked the
EEPROM is always erased by a chip erase, regardless of this bit.
| Value | Description |
|---|---|
| 0 | EEPROM erased during chip erase |
| 1 | EEPROM not erased under chip erase |