20.7.8 Interrupt Flag Register - Split Mode
Name: | INTFLAGS |
Offset: | 0x0B |
Reset: | 0x00 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
LCMP2 | LCMP1 | LCMP0 | HUNF | LUNF | |||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit 6 – LCMP2 Low-byte Compare Channel 0 Interrupt Flag
See LCMP0 flag description.
Bit 5 – LCMP1 Low-byte Compare Channel 0 Interrupt Flag
See LCMP0 flag description.
Bit 4 – LCMP0 Low-byte Compare Channel 0 Interrupt Flag
The compare interrupt flag (LCMPn) is set on a compare match on the corresponding compare channel.
For all modes of operation, the LCMPn flag will be set when a compare match occurs between the Low-byte count register (LCNT) and the corresponding compare register (LCMPn). The LCMPn flag will not be cleared automatically and has to be cleared by software. This is done by writing a ‘1’ to its bit location.
Bit 1 – HUNF High-byte Underflow Interrupt Flag
This flag is set on a high-byte timer BOTTOM (underflow) condition. HUNF is not automatically cleared and needs to be cleared by software. This is done by writing a ‘1’ to its bit location.
Bit 0 – LUNF Low-byte Underflow Interrupt Flag
This flag is set on a low-byte timer BOTTOM (underflow) condition. LUNF is not automatically cleared and needs to be cleared by software. This is done by writing a ‘1’ to its bit location.