20.7.5 Control Register E Clear - Split Mode

The individual status bit can be cleared by writing a '1' to its bit location. This allows each bit to be cleared without use of a read-modify-write operation on a single register.

Each Status bit can be read out either by reading TCA.CTRLESET or TCA.CTRLECLR.

Name: CTRLECLR
Offset: 0x04
Reset: 0x00
Property: -

Bit 76543210 
     CMD[1:0]   
Access R/WR/W 
Reset 00 

Bits 3:2 – CMD[1:0] Command

These bits are used for software control of update, restart, and reset of the timer/counter. The command bits are always read as zero.

ValueNameDescription
0x0 NONE No command
0x1 UPDATE Force update
0x2 RESTART Force restart
0x3 RESET Force hard Reset (ignored if TC is enabled)