25.5.2 Control B


Bit	7	6	5	4	3	2	1	0
	CMP1EV	CMP0EV	CLKSEL[2:0]			WGMODE[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 7 – CMP1EV Compare 1 Event Generation

This bit field controls the waveform mode on the event output line. Writing this bit to '1' will output the waveform output on the event line instead of the compare match or overflow pulse. The WO1EN bit is ignored for the event outputs.

Value	Name	Description
0	PULSE	An event pulse is generated when there is a match or overflow
1	WAVEFORM	The event output is equal to the waveform output WO1, whatever WO1EN bit it is

Bit 6 – CMP0EV Compare 0 Event Generation

This bit field controls the waveform mode on the event output line. Writing this bit to '1' will output the waveform output on the event line instead of the compare match or overflow pulse. The WO0EN bit is ignored for the event outputs.

Value	Name	Description
0	PULSE	An event pulse is generated when there is a match or overflow
1	WAVEFORM	The event output is equal to the waveform output WO0, whatever WO0EN bit it is

Bits 5:3 – CLKSEL[2:0] Clock Select

This bit field controls the Timer/Counter clock source and cannot be changed while the Timer/Counter is enabled.


Value	Name	Description
`0x0`	CLKPER	Peripheral clock
`0x1`	EVENT	Event edge
`0x2`	OSCHF	Internal high-frequency oscillator
`0x3`	OSC32K	Internal 32kHz oscillator
`0x4`	-	Reserved
`0x5`	PLL	Phase Locked Loop
`Others`	-	Reserved

Bits 2:0 – WGMODE[2:0] Waveform Generation Mode

This bit field selects the Waveform mode.

Value	Name	Description
0x0	FRQ	Frequency
0x1	NCOPF	Numerical Controlled Oscillator Pulse-Frequency
0x2	NCOFDC	Numerical Controlled Oscillator Fixed Duty-Cycle
0x3-0x6	-	Reserved
0x7	PWM8	8-Bit PWM mode

Name:	CTRLB
Offset:	0x01
Reset:	0x00
Property:	Enable-protected