25.5.8 Status
| Name: | STATUS |
| Offset: | 0x07 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CMP1BUSY | CMP0BUSY | PERBUSY | CNTBUSY | CTRLDBUSY | CTRLCBUSY | CTRLABUSY | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – CMP1BUSY Compare 1 Synchronization Busy
When this bit is '1', the TCFn is busy synchronizing the CMP1
(TCFn.CMP1) register in the asynchronous domain. This bit is valid only in the
PWM8 mode. For other modes, this bit is identical to CMP0BUSY.
Bit 6 – CMP0BUSY Compare 0 Synchronization Busy
When this bit is '1', the TCFn is busy synchronizing the Compare
(TCFn.CMP) register in the asynchronous domain.
Bit 5 – PERBUSY Period Synchronization Busy
When this bit is '1', the TCFn is busy synchronizing the Period
(TCFn.PER or TCFn.CNT1) register in the asynchronous domain. This bit in only
valid in PWM8 mode. For other modes, this bit is identical to CNTBUSY.
Bit 4 – CNTBUSY Counter Synchronization Busy
When this bit is '1', the TCFn is busy synchronizing the Counter
(TCFn.CNT) register in the asynchronous domain. After wake-up from a sleep mode
where the peripheral clock is disabled, this bit is set until the
synchronization is complete.
Bit 3 – CTRLDBUSY Control D Synchronization Busy
When this bit is '1', the TCFn is busy synchronizing the Control
D (TCFn.CTRLD) register in the asynchronous domain.
Bit 2 – CTRLCBUSY Control C Synchronization Busy
When this bit is '1', the TCFn is busy synchronizing the Control
C (TCFn.CTRLC) register in the asynchronous domain.
Bit 1 – CTRLABUSY Control A Synchronization Busy
When this bit is '1', the TCFn is busy synchronizing the Control
A (TCFn.CTRLA) register in the asynchronous domain.