25.5.11 Compare Register

The TCFn.CMP0, TCFn.CMP1, TCFn.CMP2 and TCFn.CMP3 registers represent the 32-bit value TCFn.CMP. Byte 0 [7:0] is accessible at the original offset. Byte 1 [15:8] is accessible at the offset + 0x1. Byte 2 [23:16] is accessible at the offset + 0x2. Byte 3 [31:24] is accessible at the offset + 0x3, but it never contains any data.

A write or read access to byte 2 (offset + 0x2) triggers a new synchronization.

In the 8-bit PWM mode, only TCFn.CMP0 and TCFn.CMP1 are used and accessed as independent registers. TCFn.CMP2 and TCFn.CMP3 do not have any function in this mode.

Name: CMP
Offset: 0x14
Reset: 0x00
Property: Double-Buffered

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 CMP[23:16] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 CMP[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 CMP[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 23:0 – CMP[23:0] Compare Value

This bit field holds the compare, top or increment value.