44.4.4 Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications

Figure 44-7. Reset, Watchdog Timer, and Power-up Timer Timing
Note:
  1. Asserted low.
Figure 44-8. Brown-out Reset Timing and Characteristics
Note:
  1. Only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0.
Table 44-10. 
Standard Operating Conditions (unless otherwise stated)
Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions
RST01* TMCLR MCLR Pulse-Width Low to ensure Reset — — — μs
RST02* TIOZ I/O high-impedance from Reset detection — — 2 μs
RST03 TWDT Watchdog Timer Time-out Period — 16 — ms WDTCPS = 00100
RST04* TPWRT Power-up Timer Period — 65 — ms
RST05 TOST Oscillator Start-up Timer Period(1,2) — 1024 — TOSC
RST06 VBOR Brown-out Reset Voltage

—

—

2.65

1.9

—

—

V

V

BORV = 0

BORV = 1
RST07 VBORHYS Brown-out Reset Hysteresis — 60 — mV BORV = 0
RST08 TBORDC Brown-out Reset Response Time — 3 — μs
RST09 VLPBOR Low-Power Brown-out Reset Voltage 1.8 1.9 2.2 V

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note:
  1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
  2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.