28.8.1 Control A

Name:	CTRLA
Offset:	0x00
Reset:	0x00
Property:	PAC Write-Protection, Write-Synchronized


Bit	7	6	5	4	3	2	1	0
				CKSEL			ENABLE	SWRST
Access				RW			RW	W
Reset				0			0	0

Bit 4 – CKSEL Clock Selection

The EIC can be clocked either by GCLK_EIC (when a frequency higher than 32.768 KHz is required for filtering) or by 32KHz_LPCLK (when power consumption is the priority).

This bit is not Write-Synchronized.

Value	Description
0	The EIC is clocked by GCLK_EIC.
1	The EIC is clocked by 32KHz_LPCLK.

Bit 1 – ENABLE Enable

Due to synchronization, there is a delay between writing to CTRLA.ENABLE until the peripheral is enabled/disabled. The value written to CTRLA.ENABLE will read back immediately and the Enable bit in the Synchronization Busy register is set (SYNCBUSY.ENABLE=1). SYNCBUSY.ENABLE is cleared when the operation is complete.

Note: Access to registers/bits are disallowed until the hardware clears the SYNCBUSY.ENABLE register. The SYNCBUSY.ENABLE bit is functional for Level Detection and Asynchronous Edge Detection modes. For Synchronous Edge Detection mode, it is necessary to wait for three cycles of the selected clock after enabling the EIC.

This bit is not Enable-Protected.

This bit is Write-Synchronized.

Value	Description
0	The EIC is disabled.
1	The EIC is enabled.

Bit 0 – SWRST Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets all registers in the EIC to their initial state, and the EIC is disabled.

Writing a ‘1’ to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write operation are discarded.

Due to synchronization, there is a delay from writing CTRLA.SWRST until the Reset is complete. CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the Reset is complete.

This bit is not Enable-Protected.

This bit is Write-Synchronized.

Value	Description
0	There is no ongoing reset operation.
1	The reset operation is ongoing.