35.10.10 Address

Name:	ADDR
Offset:	0x24
Reset:	0x0000
Property:	Write-Synchronized


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	LEN[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			LENEN			ADDR[10:8]
Access			R/W			R/W	R/W	R/W
Reset			0			0	0	0


Bit	7	6	5	4	3	2	1	0
	ADDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 23:16 – LEN[7:0] Transaction Length

These bits define the transaction length of a DMA and/or 32-bit transaction from 0-255 bytes. The Transfer Length Enable (LENEN) bit must be written to ‘1’ to use DMA.

Bit 13 – LENEN Transfer Length Enable

Value	Description
0	Automatic transfer length disabled.
1	Automatic transfer length enabled.

Bits 10:0 – ADDR[10:0] Address

When ADDR is written, the consecutive operation depends on the Bus state:

Table 35-6.
State	Description
UNKNOWN	INTFLAG.MB and STATUS.BUSERR are set and the operation is terminated.
BUSY	The I²C host awaits further operation until the bus becomes IDLE.
IDLE	The I²C host issues a start condition followed by the address written in ADDR. If the address is acknowledged, SCL is forced and held low and STATUS.CLKHOLD and INTFLAG.MB are set.
OWNER	A repeated start sequence is performed. If the previous transaction was a read, the acknowledge action is sent before the repeated start bus condition is issued on the bus. Writing ADDR to issue a repeated start is performed while INTFLAG.MB or INTFLAG.SB is set.
Note: STATUS.BUSERR, STATUS.ARBLOST, INTFLAG.MB and INTFLAG.SB is cleared when ADDR is written.

The ADDR register can be read at any time without interfering with ongoing bus activity, as a read access does not trigger the host logic to perform any bus protocol related operations.

The I²C host control logic uses bit ‘0’ of ADDR as the bus protocol’s read/write flag (R/W); ‘0’ for write and ‘1’ for read.