45.2 Features

Compatible with IEEE Standard 802.3

10 and 100 Mbps Operation

Full and Half Duplex Operation at all Supported Speeds of Operation

Statistics Counter Registers for RMON/MIB

RMII Interfaces to the Physical Layer

Direct Memory Access (DMA) Interface to External Memory

Support for 5 Priority Queues in DMA

Programmable Burst Length and Endianism for DMA

Interrupt Generation to Signal Receive and Transmit Completion, Errors or Other Events

Automatic Pad and Cyclic Redundancy Check (CRC) Generation on Transmitted Frames

Automatic Discard of Frames Received with Errors

Receive and Transmit IP, TCP and UDP Checksum Offload. Both IPv4 and IPv6 Packet Types Supported.

Address Checking Logic for Four Specific 48-bit Addresses, Four Type IDs, Promiscuous Mode, Hash Matching of Unicast and Multicast Destination Addresses and Wake-on-LAN

Management Data Input/Output (MDIO) Interface for Physical Layer Management

Support for Jumbo Frames Up To 3840 Bytes

Full Duplex Flow Control With Recognition of Incoming Pause Frames and Hardware Generation of Transmitted Pause Frames

Half Duplex Flow Control By Forcing Collisions on Incoming Frames

Support for 802.1Q VLAN Tagging With Recognition of Incoming VLAN and Priority Tagged Frames

Programmable Inter Packet Gap (IPG) Stretch

Recognition of IEEE 1588 PTP Frames

IEEE 1588 Time Stamp Unit (TSU)

Support for 802.1AS Timing and Synchronization

Support for 802.3az Energy Efficient Ethernet