41.10.3 Control B Set

Name: CTRLBSET
Offset: 0x05
Reset: 0x00
Property: PAC Write-Protection, Read-synchronized, Write-Synchronized

Bit 76543210 
 CMD[2:0]  ONESHOTLUPDDIR 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 7:5 – CMD[2:0] Command

These bits are used for software control of the TC. The commands are executed on the next prescaled GCLK_TC clock cycle. When a command is executed, the CMD bit group is read back as 0.

Writing 0x0 to these bits has no effect.

Writing a value different from 0x0 to these bits issues a command for execution.
Important: This command requires synchronization before executing it. The following is a valid sequence:
  • Issue CMD command (CTRLBSET.CMD = command)
  • Wait for CMD synchronization (SYNCBUSY.CTRLB = 0)
  • Wait for CMD read back as zero (CTRLBSET.CMD = 0)
ValueNameDescription
0x0NONENo action
0x1RETRIGGERForce a start, restart or retrigger
0x2STOPForce a stop
0x3UPDATEForce update of double buffered registers
0x4READSYNCForce a read synchronization of COUNT

Bit 2 – ONESHOT One-Shot on Counter

This bit controls one-shot operation of the TC.

Writing a 0 to this bit has no effect.

Writing a 1 to this bit enables one-shot operation.

ValueDescription
0The TC wraps around and continue counting on an overflow/underflow condition.
1The TC wraps around and stop on the next underflow/overflow condition.

Bit 1 – LUPD Lock Update

This bit controls the update operation of the TC buffered registers.

When CTRLB.LUPD is set, no update of the registers with a value of its buffered register is performed on the hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before a hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.

Writing a 0 to this bit has no effect.

Writing a 1 to this bit sets the LUPD bit.

This bit has no effect when input capture operation is enabled.

ValueDescription
0The CCBUFx and PERBUF buffer registers value are copied into CCx and PER registers on hardware update condition.
1The CCBUFx and PERBUF buffer registers value are not copied into CCx and PER registers on hardware update condition.

Bit 0 – DIR Counter Direction

This bit is used to change the direction of the counter.

Writing a 0 to this bit has no effect.

Writing a 1 to this bit sets the bit and make the counter count down.

ValueDescription
0The timer/counter is counting up (incrementing)
1The timer/counter is counting down (decrementing)