27.8.16 Channel Control A

Name:	CHCTRLA
Offset:	0x40 + n*0x10 [n=0..15]
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-Protected


Bit	31	30	29	28	27	26	25	24
			THRESHOLD[1:0]		BURSTLEN[3:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
			TRIGACT[1:0]
Access			R/W	R/W
Reset			0	0


Bit	15	14	13	12	11	10	9	8
	TRIGSRC[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		RUNSTDBY					ENABLE	SWRST
Access		R/W					R/W	R/W
Reset		0					0	0

Bits 29:28 – THRESHOLD[1:0] FIFO Threshold

These bits define the threshold from where the DMA starts to write to the destination. These bits have no effect in the case of single beat transfers.

These bits are not enable-protected.

Value	Name	Description
0x0	1BEAT	Destination write starts after each beat source addess read
0x1	2BEATS	Destination write starts after 2-beats source address read
0x2	4BEATS	Destination write starts after 4-beats source address read
0x3	8BEATS	Destination write starts after 8-beats source address read

Bits 27:24 – BURSTLEN[3:0] Burst Length

These bits define the burst mode.

These bits are not enable-protected.

Value	Name	Description
0x0	SINGLE	Single-beat burst
0x1	2BEAT	2-beats burst length
0x2	3BEAT	3-beats burst length
0x3	4BEAT	4-beats burst length
0x4	5BEAT	5-beats burst length
0x5	6BEAT	6-beats burst length
0x6	7BEAT	7-beats burst length
0x7	8BEAT	8-beats burst length
0x8	9BEAT	9-beats burst length
0x9	10BEAT	10-beats burst length
0xA	11BEAT	11-beats burst length
0xB	12BEAT	12-beats burst length
0xC	13BEAT	13-beats burst length
0xD	14BEAT	14-beats burst length
0xE	15BEAT	15-beats burst length
0xF	16BEAT	16-beats burst length

Bits 21:20 – TRIGACT[1:0] Trigger Action

These bits define the trigger action used for a transfer.

These bits are not enable-protected.

Value	Name	Description
0x0	BLOCK	One trigger required for each block transfer
0x1	—	Reserved
0x2	BURST	One trigger required for each burst transfer
0x3	TRANSACTION	One trigger required for each transaction

Bits 15:8 – TRIGSRC[7:0] Trigger Source

These bits define the peripheral that will be the source of a trigger.

Table 27-2. Triggers Map
TRIGSRC[7:0]	Trigger
0	DISABLE; Only software/event triggers
1	RTC_DMAC_ID_TIMESTAMP
2	DSU_DMAC_ID_DCC0
3	DSU_DMAC_ID_DCC1
4	SERCOM0_DMAC_ID_RX
5	SERCOM0_DMAC_ID_TX
6	SERCOM1_DMAC_ID_RX
7	SERCOM1_DMAC_ID_TX
8	SERCOM2_DMAC_ID_RX
9	SERCOM2_DMAC_ID_TX
10	SERCOM3_DMAC_ID_RX
11	SERCOM3_DMAC_ID_TX
12	SERCOM4_DMAC_ID_RX
13	SERCOM4_DMAC_ID_TX
14	SERCOM5_DMAC_ID_RX
15	SERCOM5_DMAC_ID_TX
16	SERCOM6_DMAC_ID_RX
17	SERCOM6_DMAC_ID_TX
18	TCC0_DMAC_ID_OVF
19	TCC0_DMAC_ID_MC_0
20	TCC0_DMAC_ID_MC_1
21	TCC0_DMAC_ID_MC_2
22	TCC0_DMAC_ID_MC_3
23	TCC0_DMAC_ID_MC_4
24	TCC0_DMAC_ID_MC_5
25	TCC1_DMAC_ID_OVF
26	TCC1_DMAC_ID_MC_0
27	TCC1_DMAC_ID_MC_1
28	TCC1_DMAC_ID_MC_2
29	TCC1_DMAC_ID_MC_3
30	TCC1_DMAC_ID_MC_4
31	TCC1_DMAC_ID_MC_5
32	TCC2_DMAC_ID_OVF
33	TCC2_DMAC_ID_MC_0
34	TCC2_DMAC_ID_MC_1
35	TC0_DMAC_ID_OVF
36	TC0_DMAC_ID_MC_0
37	TC0_DMAC_ID_MC_1
38	TC1_DMAC_ID_OVF
39	TC1_DMAC_ID_MC_0
40	TC1_DMAC_ID_MC_1
41	TC2_DMAC_ID_OVF
42	TC2_DMAC_ID_MC_0
43	TC2_DMAC_ID_MC_1
44	TC3_DMAC_ID_OVF
45	TC3_DMAC_ID_MC_0
46	TC3_DMAC_ID_MC_1
47	TC4_DMAC_ID_OVF
48	TC4_DMAC_ID_MC_0
49	TC4_DMAC_ID_MC_1
50	TC5_DMAC_ID_OVF
51	TC5_DMAC_ID_MC_0
52	TC5_DMAC_ID_MC_1
53	TC6_DMAC_ID_OVF
54	TC6_DMAC_ID_MC_0
55	TC6_DMAC_ID_MC_1
56	TC7_DMAC_ID_OVF
57	TC7_DMAC_ID_MC_0
58	TC7_DMAC_ID_MC_1
59	TC8_DMAC_ID_OVF
60	TC8_DMAC_ID_MC_0
61	TC8_DMAC_ID_MC_1
62	TC9_DMAC_ID_OVF
63	TC9_DMAC_ID_MC_0
64	TC9_DMAC_ID_MC_1
65	QSPI_DMAC_ID_RX
66	QSPI_DMAC_ID_TX
67	CAN0_DMAC_ID_DBGMSG
68	CAN1_DMAC_ID_DBGMSG

Bit 6 – RUNSTDBY Channel run in standby

This bit is used to keep the DMAC channel running in Idle and Standby Sleep mode.

This bit is not enable-protected.

Value	Description
0	The DMAC channel is halted in Idle and Standby Sleep mode.
1	The DMAC channel continues to run in Idle and Standby Sleep mode.

Bit 1 – ENABLE Channel Enable

When writing a ‘0’ to this bit during an ongoing transfer, the bit must not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The internal data transfer buffer is empty when the ongoing burst transfer is completed.

Writing a ‘1’ to this bit enables the DMA channel.

This bit is not enable-protected.

Value	Description
0	DMA channel is disabled.
1	DMA channel is enabled.

Bit 0 – SWRST Channel Software Reset

Writing a ‘0’ to this bit has no effect.

Writing a ‘1’ to this bit resets the channel registers to their initial state. The bit can be set when the channel is disabled (ENABLE=0). Writing a ‘1’ to this bit is ignored as long as ENABLE=1. This bit is automatically cleared when the reset is completed.

Value	Description
0	There is no reset operation ongoing.
1	The reset operation is ongoing.