23.2 Features
This PIC32CX-BZ6 device provides several user-writable configuration registers related to the configuration and operation of the system.
- Permission Group Configuration Register (CFGPG) Defines the Permission Group
- System Key Register (SYSKEY) Defines the System Key
- Configuration Control Register 0 (CFGCON0(L)) Provides Control, Selection and Locking for Various Features of the DeviceNote: The registers marked with (L) are loadable from Flash.
- PPS register locking
- PMD register locking
- CFGPG register locking
- Config register locking
- PMU controller register locking
- Trace port enable, JTAG enable, SWO enable
- Flash, SRAM ECC control
- RTCC, AC alternate pinout selection
- USB Functions
-
INT0 control
-
SMBus3 enable
- Configuration Control Register 1 (CFGCON1(L)) Provides Control, Selection and Locking for Various Features of the Device
- QSPI DDR mode clock and address space cache enable
- High-speed SERCOM, QSPI enable
- WDT Sleep mode prescale configuration
- CAN pins enable/disable
- Debug port configuration and enable
-
USB DP DM rise/fall trim
-
AC1, AC0, CCL_OE output enable
-
MCLR configuration
- Configuration Control Register 2 (CFGCON2(L)) Provides Control, Selection and Locking for Various Features of the Device
- DMT enable and configuration
- WDT enable and configuration
- Clock monitoring and control
- Oscillator enable and configuration
- Two-speed start-up enabled in Sleep mode bit
- Configuration Control Register 4 (CFGCON4(L)) Provides Control, Selection and Locking for Various Features of the Device
- Deep sleep modules control
- SOSC configuration control
- RTCC event control and clock select
- CFGI2C Register provides control for I2C slew rate control, I2C delay enable, and SMBus enable
- CFGCLKGENx Registers Provides Clock Selection for Peripherals
- User Unique ID Register (USERID(L)) Provides the End User with a 16-Bit ID Field that Can be Read Out Directly Through the SWD Interface Via the USERID SWD Instruction