8.3 Power Management Unit
The Microchip SAMA7D65 System-On-Module Series is supplied by an external 5V supply (5V_MAIN) and generates its own internal supplies by interfacing with the Microchip MCP16502 power management unit.
The MCP16502 is a fully-featured Power Management Integrated Circuit (PMIC), cost and size-optimized for Microchip MPU devices such as the SAMA7D65 SiP.
The MCP16502 PMIC integrates four DC-DC buck regulators used for system supply and two auxiliary LDOs for customer purposes.
- All buck channels can support
loads up to 1A. All bucks are 100% duty-cycle capable.
- DCDC1, set to 3.3 V, supplies all pads of the embedded devices. This power rail offers a 600 mA load to customer applications through VDD_3V3 (pins 156, 157).
- DCDC2, set to 1.35V, supplies the DDR3L memory. It is used internally only.
- DCDC3, set to 1.15V, supplies the microprocessor core. It is used internally only.
- DCDC4, set to 1.15V, supplies the microprocessor CPU. It is used internally only.
- One 300 mA LDO is provided so that sensitive analog loads can be supported. The LDO output voltage, named VLDO1 (pin 175), is configured by a three-state signal named SEL_VLDO1 (pin 166) at power-up and can deliver 1.8V, 2.5V or 3.3V. Other voltage values can be reached after system initialization by an I²C interface access.
- One 300 mA LDO is provided so that sensitive analog loads can be supported. The LDO output voltage, named VLDO2 (pin 176), is disabled by default at power-up. Output voltage values are set through an I²C interface access after system initialization.
The default power channel sequencing is built-in as required by the Microchip SAMA7D65 MPU device.
Active discharge resistors are provided on each output. All buck channels support safe start-up into pre-biased outputs.
The MCP16502 is available in a 5 mm x 5 mm 32-pin VQFN package.
For more information, refer to the MCP16502 PMIC data sheet (see Reference Documents).
The VLDO1 voltage output of the LDO is controlled at boot by configuration of SEL_VLDO1 (pin 166). The default values are selectable among three options corresponding to three different states of the relevant pin: connected to ground (Low), connected to input supply (High) or left unconnected (High-Z). The VLDO1 default voltage can be selected by means of the SEL_VLDO1 pin, as shown in the table below.
| SEL_VLDO1 Status | VLDO1 Voltage |
|---|---|
| Low (grounded) | 1.8V |
| High-Z (not connected) | 2.5V |
| High (up to 5V_MAIN) | 3.3V |
The LPM pin of the Microchip SAMA7D65 System-On-Module Series, combined with the HPM and PWRHLD status pins of the MCP16502 PMIC, defines different power states as illustrated in the table below.
| PWRHLD | LPM | HPM | Buck1 | Buck2 | Buck3 | Buck4 | LDO1 | LDO2 | nRST | Power State(1) |
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | Off | Off | Off | Off | Off | Off | Low | Off |
| 0 | 1 | 0 | Off | On(2) | Off | On(2) | Off | Off | Low | Hibernate mode |
| 1 | 1 | 0 | On(2) | On(2) | On(2) | On(2) | On | Off | HiZ | Low-Power mode |
| 1 | 0 | 0 | On(3) | On(3) | On(3) | On(3) | On | Off | HiZ | Active mode |
| 1 | 0 | 1 | On(3) | On(3) | On(3) | On(3) | On | Off | HiZ | High-Performance Active |
- Only allowed modes are listed. If some PWRHLD/LPM/HPM combination is not listed, the mode is not allowed.
- In this mode, the DCDC is configured in Automatic Pulse-Frequency Modulation (Auto-PFM) mode.
- In this mode, the DCDC is configured in Force Pulse-Width Modulation (FPWM) mode.
For more information about the use of the MCP16502 PMIC LPM feature, refer to the MCP16502 data sheet (see Reference Documents).