4.1 In-System Programming

(Ask a Question)

In-System Programming is performed with the aid of external JTAG programming hardware. Table 4-1 describes the JTAG programming hardware that will program a SmartFusion cSoC and Table 4-2 defines the JTAG pins that provide the interface for the programming hardware.

Table 4-1. Supported JTAG Programming Hardware
Dongle	Source	JTAG	SWD¹	SWV²	Program FPGA	Program eFROM	Program eNVM
FlashPro3/4	SoC Products Group	Yes	No	No	Yes	Yes	Yes
ULINK Pro	Keil	Yes	Yes	Yes	Yes³	Yes³	Yes
ULINK2	Keil	Yes	Yes	Yes	Yes³	Yes³	Yes
IAR J-Link	IAR	Yes	Yes	Yes	Yes³	Yes³	Yes

Note:

SWD = ARM Serial Wire Debug
SWV = ARM Serial Wire Viewer
Planned support

Table 4-2. JTAG Pin Descriptions
Pin Name	Description
JTAGSEL	ARM Cortex®-M3 or FPGA test access port (TAP) controller selection
TRSTB	Test reset bar
TCK	Test clock
TMS	Test mode select
TDI	Test data input
TDO	Test data output

The JTAGSEL pin selects the FPGA TAP controller or the Cortex-M3 debug logic. When JTAGSEL is asserted, the FPGA TAP controller is selected and the TRSTB input into the Cortex-M3 is held in a reset state (logic 0), as depicted in the following figure. Users should tie the JTAGSEL pin high externally.

Microchip’s free Eclipse-based IDE, SoftConsole, has the ability to control the JTAGSEL pin directly with the FlashPro4 programmer. Manual jumpers are provided on the evaluation and development kits to allow manual selection of this function for the J-Link and ULINK debuggers.

Standard ARM JTAG connectors do not have access to the JTAGSEL pin. SoftConsole automatically selects the appropriate TAP controller using the CTXSELECT JTAG command. When using SoftConsole, the state of JTAGSEL is a “don't care.”