Operating Conditions- 2.5V-3.6V, -40°C
to +85°C, DC to 300 MHz
- 2.5V-3.6V, -40°C
to +105°C, DC to 300 MHz
Qualification- AEC - Q100 Grade
2 (-40°C to +105°C)
Core- Arm® Cortex®-M7 running at up to
300 MHz
- 16 KB of I-Cache
and 16 KB of D-Cache with Error Code Correction (ECC)
- Single-precision
and double-precision HW Floating Point Unit (FPU)
- Memory Protection
Unit (MPU) with 16 zones
- DSP Instructions,
Thumb®-2 Instruction Set
- Embedded Trace
Module (ETM) with instruction trace stream, including Trace Port
Interface Unit (TPIU)
Memories- 2048 KB embedded Flash with unique identifier and user signature
for user-defined data
- Up to 512 KB embedded Multi-port SRAM
- Up to 256 KB Tightly Coupled Memory (TCM)
- 16 KB ROM with In-Application Programming (IAP) routines
- One External Bus Interface (EBI) (optional) containing a 16-bit
Static Memory Controller (SMC) with support for SRAM, PSRAM, LCD
module, NOR and NAND Flash with on-the-fly scrambling
| Cryptography- True Random
Number Generator (TRNG)
- AES: 256-bit,
192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB-197
Specifications
- Integrity Check
Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224, and
SHA256.
System- Embedded voltage regulator for single-supply operation
- Power-on-Reset (POR), Brown-out Detector (BOD) and Dual Watchdog
for safe operation
- RTC with Gregorian calendar mode, waveform generation in
low-power modes
- RTC counter calibration circuitry compensates for 32.768 kHz
crystal frequency variations
- 32-bit low-power Real-Time Timer (RTT)
- Temperature Sensor
- One dual-port 24-channel central DMA Controller (XDMAC)
Power Management- Single or Dual
Power Supply capability
Clock Management- Quartz or ceramic
resonator oscillators: 3 MHz to 20 MHz main oscillator with
failure detection, 12 MHz or 16 MHz needed for USB operations.
Optional low-power 32.768 kHz for RTC or device clock
- High-precision
Main RC oscillator with 12 MHz default frequency
- 32.768 kHz
crystal oscillator or Slow RC oscillator as source of low-power
mode device clock (SLOW_CLK)
- One 500 MHz PLL
for system clock
- One 480 MHz PLL
for USB high-speed operations
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Communication Interfaces- One (optional)
Ethernet MAC (GMAC)
- 10/100
Mbps in MII and RMII with dedicated DMA
- IEEE® 1588 PTP frames support
- IEEE
802.1AS Timestamping support
- IEEE
802.1Qav credit-based traffic shaping hardware
support
- 802.3az energy efficient support
- Ethernet AVB support
- USB 2.0
Device/Mini Host High-speed (USBHS) at 480 Mbps, 4-KB FIFO, up
to 10 bidirectional endpoints, dedicated DMA
- 12-bit ITU-R BT.
601/656 Image Sensor Interface (ISI).
- Up to two host
Controller Area Networks (MCAN) with Flexible Data Rate (CAN-FD)
with SRAM-based mailboxes, time-triggered and event-triggered
transmission
- MediaLB® device (optional) with 3-wire mode, up to 1024
x Fs speed, supporting MOST25 and MOST50 networks
- Up to three USART
with LIN, ISO7816, IrDA®, RS-485, SPI, Manchester, Modem and LON
(USART1 only) modes support
- Up to five 2-wire
UARTs with SleepWalking™ support
- Up to three
Two-Wire Interfaces (TWIHS) (I2C-compatible) with
SleepWalking support
- Quad I/O Serial
Peripheral Interface (QSPI) interfacing up to 256 MB Flash and
with eXecute-In-Place and on-the-fly scrambling
- Up to two Serial
Peripheral Interfaces (SPI)
- One Serial
Synchronous Controller (SSC) with I2S and TDM
support
- Up to two
Inter-IC Sound Controllers (I2SC)
- One High-speed
Multimedia Card Interface (HSMCI) (SDIO/SD Card/e.MMC)
(optional)
| Timers/Output Compare/Input Capture- Four 3-Channel
16-bit Timer/Counters (TC) with Capture, Waveform, Compare and
PWM modes, constant on time. Quadrature decoder logic and 2-bit
Gray Up/Down Counter for stepper motor
- Two 4-channel
16-bit PWMs with complementary outputs, Dead Time Generator and
eight fault inputs per PWM for motor control, two external
triggers to manage power factor correction (PFC), DC-DC and
lighting control
Advanced Analog and Touch - Two Analog
Front-End Controllers (AFEC), total supporting up to 24 channels
with differential input mode and programmable gain stage,
allowing dual Sample-and-Hold (S/H) at up to 1.7 Msps. Offset
and gain error correction feature.
- One 12 bit, up to
2 channel, 1 Msps per channel Digital-to-Analog Controller (DAC)
with Differential and Over-Sampling modes
- One Analog
Comparator Controller (ACC) with flexible input selection,
selectable input hysteresis
I/O- Up to 114 I/O
lines with external interrupt capability (edge sensitivity or
level sensitivity), debouncing, glitch filtering and On-die
Series Resistor Termination
- Five Parallel Input/Output Controllers (PIO)
Low-Power Features- Low-power sleep,
wait, and backup modes, with typical power consumption down to
1.6 μA in Backup mode with RTC, RTT and wakeup logic
enabled
- Ultra low-power RTC and RTT
- 1 KB of backup RAM (BRAM) with dedicated regulator
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