49.3 Block Diagram

Table 49-1. Timer Counter Clock Assignment
NameDefinition
TIMER_CLOCK1PCK6 or PCK7 (TC0 only)
TIMER_CLOCK2MAIN_CLK/8
TIMER_CLOCK3MAIN_CLK/32
TIMER_CLOCK4MAIN_CLK/128
TIMER_CLOCK5 (1) SLOW_CLK
  1. When SLOW_CLK is selected for Peripheral Clock (CSS = 0 in PMC Host Clock register), SLOW_CLK input is equivalent to Peripheral Clock.
  2. The PCK6 or PCK7 (TC0 only) frequency must be at least 2.5 times lower than the peripheral clock frequency.
Figure 49-1. Timer Counter Module N Block Diagram (N = 0,1,2,3)
Note: The QDEC connections are detailed in "Predefined Connection of the Quadrature Decoder with Timer Counters".
Table 49-2. Channel Signal Description
Signal NameDescription
XC0, XC1, XC2External clock inputs
TIOAxCapture mode: Timer Counter Input
 Waveform Mode: Timer Counter Output
TIOBxCapture mode: Timer Counter Input
Waveform Mode: Timer Counter Input/Output
INTInterrupt signal output (internal signal)
SYNCSynchronization input signal (from configuration register)