28.7 Baud Rate Generator

The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register. When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down.

Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state.

An internal signal “Reload”, shown in Figure 28-40, triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode in which the MSSP is being operated.

Table 28-1 illustrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD.

MSSP Baud Rate Generator Frequency Equation

F C L O C K = F O S C 4 × ( S S P x A D D + 1 )

Figure 28-40. Baud Rate Generator Block Diagram
Important: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation.
Table 28-1. MSSP Clock Rate w/BRG
FOSC FCY BRG Value Fclock 
(2 Rollovers of BRG)
32 MHz 8 MHz 13h 400 kHz
32 MHz 8 MHz 19h 308 kHz
32 MHz 8 MHz 4Fh 100 kHz
16 MHz 4 MHz 09h 400 kHz
16 MHz 4 MHz 0Ch 308 kHz
16 MHz 4 MHz 27h 100 kHz
4 MHz 1 MHz 09h 100 kHz
Note: Refer to the I/O port electrical specifications in the “Electrical Specifications” section, Internal Oscillator Parameters, to ensure the system is designed to support all requirements.