38.1 Standard Instruction Set

The standard PIC18 instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from these PIC® MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations.

Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction.

The instruction set is highly orthogonal and is grouped into four basic categories:

  • Byte-oriented operations
  • Bit-oriented operations
  • Literal operations
  • Control operations

The PIC18 instruction set summary in Table 38-2 lists byte-oriented, bit-oriented, literal and control operations. Table 38-1 shows the opcode field descriptions.

Most byte-oriented instructions have three operands:

  1. The file register (specified by ‘f’)
  2. The destination of the result (specified by ‘d’)
  3. The accessed memory (specified by ‘a’)

The file register designator ‘f’ specifies which file register is to be used by the instruction. The destination designator ‘d’ specifies where the result of the operation is to be placed. If ‘d’ is zero, the result is placed in the WREG register. If ‘d’ is one, the result is placed in the file register specified in the instruction.

All bit-oriented instructions have three operands:

  1. The file register (specified by ‘f’)
  2. The bit in the file register (specified by ‘b’)
  3. The accessed memory (specified by ‘a’)

The bit field designator ‘b’ selects the number of the bit affected by the operation, while the file register designator ‘f’ represents the number of the file in which the bit is located.

The literal instructions may use some of the following operands:

  • A literal value to be loaded into a file register (specified by ‘k’)
  • The desired FSR register to load the literal value into (specified by ‘f’)
  • No operand required 
(specified by ‘—’)

The control instructions may use some of the following operands:

  • A program memory address (specified by ‘n’)
  • The mode of the CALL or RETURN instructions 
(specified by ‘s’)
  • The mode of the table read and table write instructions (specified by ‘m’)
  • No operand required 
(specified by ‘—’)

All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the four MSbs are ‘1’s. If this second word is executed as an instruction (by itself), it will execute as a NOP.

All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP.

The double-word instructions execute in two instruction cycles.

One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 μs. If a conditional test is true, or the Program Counter is changed as a result of an instruction, the instruction execution time is 2 μs. Two-word branch instructions (if true) would take 3 μs.

Figure 38-1 shows the general formats that the instructions can have. All examples use the convention ‘nnh’ to represent a hexadecimal number.

The Instruction Set Summary, shown in Table 38-2, lists the standard instructions recognized by the Microchip Assembler (MPASMTM).

38.1.1 Standard Instruction Set
 provides a description of each instruction.

Table 38-1. Opcode Field Descriptions
Field Description
a
RAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb
Bit address within an 8-bit file register (0 to 7).
BSR
Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N
ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
d
Destination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest Destination: either the WREG register or the specified register file location.
f
8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs
12-bit Register file address (000h to FFFh). This is the source address.
fd
12-bit Register file address (000h to FFFh). This is the destination address.
GIE
Global Interrupt Enable bit.
k
Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label
Label name.
mm
The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
* No change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (such as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
n
The relative address (2’s complement number) for relative branch instructions or the direct address for 
CALL/BRANCH and RETURN instructions.
PC
Program Counter.
PCL
Program Counter Low Byte.
PCH
Program Counter High Byte.
PCLATH
Program Counter High Byte Latch.
PCLATU
Program Counter Upper Byte Latch.
PD
Power-down bit.
PRODH
Product of Multiply High Byte.
PRODL
Product of Multiply Low Byte.
s
Fast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR
21-bit Table Pointer (points to a Program Memory location).
TABLAT
8-bit Table Latch.
TO
Time-out bit.
TOS
Top-of-Stack.
u
Unused or unchanged.
WDT
Watchdog Timer.
WREG
Working register (accumulator).
x
Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.
zs
7-bit offset value for Indirect Addressing of register files (source).
zd
7-bit offset value for Indirect Addressing of register files (destination).
{ } Optional argument.
[text] Indicates an indexed address.
(text)
The contents of text.
[expr]<n>
Specifies bit n of the register indicated by the pointer expr.
Assigned to.
[ ]
Register bit field.
In the set of.
italics User defined term (font is Courier).
Figure 38-1. General Format for Instructions
Table 38-2. Instruction Set
Mnemonic,

Operands

Description Cycles 16-Bit Instruction Word Status

Affected

Notes
MSb LSb
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1
0010
01da
ffff
ffff
C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and CARRY bit to f 1
0010
00da
ffff
ffff
C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1
0001
01da
ffff
ffff
Z, N 1, 2
CLRF f, a Clear f 1
0110
101a
ffff
ffff
Z 2
COMF f, d, a Complement f 1
0001
11da
ffff
ffff
Z, N 1, 2
CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3)
0110
001a
ffff
ffff
None 4
CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3)
0110
010a
ffff
ffff
None 4
CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3)
0110
000a
ffff
ffff
None 1, 2
DECF f, d, a Decrement f 1
0000
01da
ffff
ffff
C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3)
0010
11da
ffff
ffff
None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3)
0100
11da
ffff
ffff
None 1, 2
INCF f, d, a Increment f 1
0010
10da
ffff
ffff
C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3)
0011
11da
ffff
ffff
None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3)
0100
11da
ffff
ffff
None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1
0001
00da
ffff
ffff
Z, N 1, 2
MOVF f, d, a Move f 1
0101
00da
ffff
ffff
Z, N 1
MOVFF fs, fd Move fs (source) to 1st word
 2
1100
ffff
ffff
ffff
None
fd (destination) 2nd word
1111
ffff
ffff
ffff
MOVWF f, a Move WREG to f 1
0110
111a
ffff
ffff
None
MULWF f, a Multiply WREG with f 1
0000
001a
ffff
ffff
None 1, 2
NEGF f, a Negate f 1
0110
110a
ffff
ffff
C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1
0011
01da
ffff
ffff
C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1
0100
01da
ffff
ffff
Z, N
RRCF f, d, a Rotate Right f through Carry 1
0011
00da
ffff
ffff
C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1
0100
00da
ffff
ffff
Z, N
SETF f, a Set f 1
0110
00da
ffff
ffff
None 1, 2
SUBFWB f, d, a Subtract f from WREG with 
 borrow 1
0101
01da
ffff
ffff
C, DC, Z, OV, N
SUBWF f, d, a Subtract WREG from f 1
0101
11da
ffff
ffff
C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 
 borrow 1
0101
10da
ffff
ffff
C, DC, Z, OV, N
SWAPF f, d, a Swap nibbles in f 1
0011
10da
ffff
ffff
None 4
TSTFSZ f, a Test f, skip if 0 1 (2 or 3)
0110
011a
ffff
ffff
None 1, 2

XORWF

f, d, a

Exclusive OR WREG with f

1

0001
10da
ffff
ffff

Z, N

BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1
1001
bbba
ffff
ffff
None 1, 2
BSF f, b, a Bit Set f 1
1000
bbba
ffff
ffff
None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3)
1011
bbba
ffff
ffff
None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3)
1010
bbba
ffff
ffff
None 3, 4

BTG

f, b, a

Bit Toggle f

1

0111
bbba
ffff
ffff

None

1, 2

CONTROL OPERATIONS
BC n Branch if Carry 1 (2)
1110
0010
nnnn
nnnn

None

4
BN n Branch if Negative 1 (2)
1110
0110
nnnn
nnnn

None

BNC n Branch if Not Carry 1 (2)
1110
0011
nnnn
nnnn

None

BNN n Branch if Not Negative 1 (2)
1110
0111
nnnn
nnnn

None

BNOV n Branch if Not Overflow 1 (2)
1110
0101
nnnn
nnnn

None

BNZ n Branch if Not Zero 1 (2)
1110
0001
nnnn
nnnn

None

BOV n Branch if Overflow 1 (2)
1110
0100
nnnn
nnnn

None

BRA n Branch Unconditionally 2
1101
0nnn
nnnn
nnnn

None

BZ n Branch if Zero 1 (2)
1110
0000
nnnn
nnnn

None

CALL k, s Call

subroutine 1st word

2
1110
110s
kkkk
kkkk

None

2nd word
1111
kkkk
kkkk
kkkk
CLRWDT

Clear Watchdog Timer 1
0000
0000
0000
0100
TO, PD
DAW Decimal Adjust WREG 1
0000
0000
0000
0111
C
GOTO k

Go to address 1st word

2
1110
1111
kkkk
kkkk
None
2nd word
1111
kkkk
kkkk
kkkk
NOP No Operation 1
0000
0000
0000
0000
None
NOP No Operation 1
1111
xxxx
xxxx
xxxx
None
POP

Pop top of return stack (TOS) 1
0000
0000
0000
0110
None
PUSH Push top of return stack (TOS) 1
0000
0000
0000
0101
None
RCALL n Relative Call 2
1101
1nnn
nnnn
nnnn
None
RESET Software device Reset 1
0000
0000
1111
1111
All
RETFIE s Return from interrupt enable 2
0000
0000
0001
000s

GIE/GIEH,

PEIE/GIEL

RETLW k Return with literal in WREG 2
0000
1100
kkkk
kkkk
None
RETURN s Return from Subroutine 2
0000
0000
0001
001s
None

SLEEP

Go into Standby mode

1

0000
0000
0000
0011

TO, PD

LITERAL OPERATIONS
ADDLW k Add literal and WREG 1
0000
1111
kkkk
kkkk
C, DC, Z, OV, N
ANDLW k AND literal with WREG 1
0000
1011
kkkk
kkkk
Z, N
IORLW k Inclusive OR literal with WREG 1
0000
1001
kkkk
kkkk
Z, N
LFSR f, k Move literal (12-bit) 2nd word 
 2
1110
1110
00ff
kkkk
None
to FSR(f) 1st word
1111
0000
kkkk
kkkk
MOVLB k Move literal to BSR<3:0> 1
0000
0001
0000
kkkk
None
MOVLW k Move literal to WREG 1
0000
1110
kkkk
kkkk
None
MULLW k Multiply literal with WREG 1
0000
1101
kkkk
kkkk
None
RETLW k Return with literal in WREG 2
0000
1100
kkkk
kkkk
None
SUBLW k Subtract WREG from literal 1
0000
1000
kkkk
kkkk
C, DC, Z, OV, N

XORLW

k

Exclusive OR literal with WREG

1

0000
1010
kkkk
kkkk

Z, N

DATA MEMORY ↔ PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2
0000
0000
0000
1000
None
TBLRD*+ Table Read with post-increment
0000
0000
0000
1001
None
TBLRD*- Table Read with post-decrement
0000
0000
0000
1010
None
TBLRD+* Table Read with pre-increment
0000
0000
0000
1011
None
TBLWT* Table Write 2
0000
0000
0000
1100
None
TBLWT*+ Table Write with post-increment
0000
0000
0000
1101
None
TBLWT*- Table Write with post-decrement
0000
0000
0000
1110
None

TBLWT+*

Table Write with pre-increment

0000
0000
0000
1111

None

Note:
  1. When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’.
  2. If this instruction is executed on the TMR0 register (and where applicable, ‘d’ = 1), the prescaler will be cleared if assigned.
  3. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
  4. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.