13.2 Operation

8x8 Unsigned Multiply Routine shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register.

8x8 Signed Multiply Routine shows the sequence to do an 8x8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done.

8x8 Unsigned Multiply Routine

        MOVF    ARG1, W   ;

        MULWF   ARG2      ; ARG1 * ARG2 -> PRODH:PRODL

8x8 Signed Multiply Routine

        MOVF    ARG1, W
        MULWF   ARG2       ; ARG1 * ARG2 -> PRODH:PRODL
        BTFSC   ARG2, SB   ; Test Sign Bit
        SUBWF   PRODH, F   ; PRODH = PRODH - ARG1
        MOVF    ARG2, W
        BTFSC   ARG1, SB   ; Test Sign Bit
        SUBWF   PRODH, F   ; PRODH = PRODH - ARG2
Table 13-1. Performance Comparison for Various Multiply Operations
Routine Multiply Method Program
Memory
(Words) Cycles
(Max) Time
@ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz
8x8 unsigned Without hardware multiply 13 69 4.3 μs 6.9 μs 27.6 μs 69 μs
Hardware multiply 1 1 62.5 ns 100 ns 400 ns 1 μs
8x8 signed Without hardware multiply 33 91 5.7 μs 9.1 μs 36.4 μs 91 μs
Hardware multiply 6 6 375 ns 600 ns 2.4 μs 6 μs
16x16 unsigned Without hardware multiply 21 242 15.1 μs 24.2 μs 96.8 μs 242 μs
Hardware multiply 28 28 1.8 μs 2.8 μs 11.2 μs 28 μs
16x16 signed Without hardware multiply 52 254 15.9 μs 25.4 μs 102.6 μs 254 μs
Hardware multiply 35 40 2.5 μs 4.0 μs 16.0 μs 40 μs

16 x 16 Unsigned Multiply Routine shows the sequence to do a 16 x 16 unsigned multiplication. The equation below shows the algorithm that is used. The 32-bit result is stored in four registers (RES[3:0]).

16 x 16 Unsigned Multiplication Algorithm

R E S 3 : R E S 0 = A R G 1 H : A R G 1 L • A R G 2 H : A R G 2 L = ( A R G 1 H • A R G 2 H • 2 16 ) + ( A R G 1 H • A R G 2 L • 2 8 ) + ( A R G 1 L • A R G 2 H • 2 8 ) + ( A R G 1 L • A R G 2 L )

16 x 16 Unsigned Multiply Routine

        MOVF    ARG1L, W
        MULWF   ARG2L           ; ARG1L * ARG2L → PRODH:PRODL
        MOVFF   PRODH, RES1     ;
        MOVFF   PRODL, RES0     ;
;
        MOVF    ARG1H, W        ;
        MULWF   ARG2H           ; ARG1H * ARG2H → PRODH:PRODL
        MOVFF   PRODH, RES3     ;
        MOVFF   PRODL, RES2     ;
;
        MOVF    ARG1L, W
        MULWF   ARG2H           ; ARG1L * ARG2H → PRODH:PRODL
        MOVF    PRODL, W        ;
        ADDWF   RES1, F         ; Add cross products
        MOVF    PRODH, W        ;
        ADDWFC  RES2, F         ;
        CLRF    WREG            ;
        ADDWFC  RES3, F         ;
;
        MOVF    ARG1H, W        ;
        MULWF   ARG2L           ; ARG1H * ARG2L → PRODH:PRODL
        MOVF    PRODL, W        ;
        ADDWF   RES1, F         ; Add cross products
        MOVF    PRODH, W        ; 
        ADDWFC  RES2, F         ;
        CLRF    WREG            ;
        ADDWFC  RES3, F         ;

16 x 16 Signed Multiply Routine shows the sequence to do a 16 x 16 signed multiply. The equation below shows the algorithm used. The 32-bit result is stored in four registers (RES[3:0]). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done.

16 x 16 Signed Multiplication Algorithm

R E S 3 : R E S 0 = A R G 1 H : A R G 1 L • A R G 2 H : A R G 2 L = ( A R G 1 H • A R G 2 H • 2 16 ) + ( A R G 1 H • A R G 2 L • 2 8 ) + ( A R G 1 L • A R G 2 H • 2 8 ) + ( A R G 1 L • A R G 2 L ) + ( − 1 • A R G 2 H < 7 > • A R G 1 H : A R G 1 L • 2 16 ) + ( − 1 • A R G 1 H < 7 > • A R G 2 H : A R G 2 L • 2 16 )

16 x 16 Signed Multiply Routine

        MOVF    ARG1L, W
        MULW    ARG2L           ; ARG1L * ARG2L → PRODH:PRODL 
        MOVF    PRODH, RES1     ;
        MOVFF   PRODL, RES0     ;
;
        MOVF    ARG1H, W
        MULWF   ARG2H           ; ARG1H * ARG2H → PRODH:PRODL
        MOVFF   PRODH, RES3     ;
        MOVFF   PRODL, RES2     ;
;
        MOVF    ARG1L, W
        MULWF   ARG2H           ; ARG1L * ARG2H → PRODH:PRODL
        MOVF    PRODL, W        ;
        ADDWF   RES1, F         ; Add cross products
        MOVF    PRODH, W        ;
        ADDWFC  RES2, F         ;
        CLRF    WREG            ;
        ADDWFC  RES3, F         ;
;
        MOVF    ARG1H, W        ;
        MULWF   ARG2L           ; ARG1H * ARG2L → PRODH:PRODL
        MOVF    PRODL, W        ;
        ADDWF   RES1, F         ; Add cross products
        MOVF    PRODH, W        ;
        ADDWFC  RES2, F         ;
        CLRF    WREG            ;
        ADDWFC  RES3, F         ;
;
        BTFSS   ARG2H, 7        ; ARG2H:ARG2L neg?
        BRA     SIGN_ARG1       ; no, check ARG1
        MOVF    ARG1L, W        ;
        SUBWF   RES2            ;
        MOVF    ARG1H, W        ;
        SUBWFB  RES3 
; 

SIGN_ARG1:
        BTFSS   ARG1H, 7        ; ARG1H:ARG1L neg?
        BRA     CONT_CODE       ; no, done
        MOVF    ARG2L, W        ;
        SUBWF   RES2            ;
        MOVF    ARG2H, W        ;
        SUBWFB  RES3
;
CONT_CODE:
          :