18.1 PPS Inputs
Each peripheral has an xxxPPS register with which the input pin to the peripheral is selected. Not all ports are available for input as shown in the following table.
Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must be cleared to enable the digital input buffer.
Important: The notation “xxx” in the generic register name
is a place holder for the peripheral identifier. For example, xxx = INT for the INTPPS
register.
| Peripheral | PPS Input Register | Default Pin Selection at POR | Register Reset Value at POR | PORT From Which Input Is Available | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 28-Pin Devices | 40-Pin Devices | |||||||||
| Interrupt 0 | INT0PPS | RB0 | 0x08 | A | B | — | A | B | — | — |
| Interrupt 1 | INT1PPS | RB1 | 0x09 | A | B | — | A | B | — | — |
| Interrupt 2 | INT2PPS | RB2 | 0x0A | A | B | — | A | B | — | — |
| Timer0 Clock | T0CKIPPS | RA4 | 0x04 | A | B | — | A | B | — | — |
| Timer1 Clock | T1CKIPPS | RC0 | 0x10 | A | — | C | A | — | C | — |
| Timer1 Gate | T1GPPS | RB5 | 0x0D | — | B | C | — | B | C | — |
| Timer3 Clock | T3CKIPPS | RC0 | 0x10 | — | B | C | — | B | C | — |
| Timer3 Gate | T3GPPS | RC0 | 0x10 | A | — | C | A | — | C | — |
| Timer5 Clock | T5CKIPPS | RC2 | 0x12 | A | — | C | A | — | C | — |
| Timer5 Gate | T5GPPS | RB4 | 0x0C | — | B | C | — | B | — | D |
| Timer2 Clock | T2INPPS | RC3 | 0x13 | A | — | C | A | — | C | — |
| Timer4 Clock | T4INPPS | RC5 | 0x15 | — | B | C | — | B | C | — |
| Timer6 Clock | T6INPPS | RB7 | 0x0F | — | B | C | — | B | — | D |
| ADC Conversion Trigger | ADACTPPS | RB4 | 0x0C | — | B | C | — | B | — | D |
| CCP1 | CCP1PPS | RC2 | 0x12 | — | B | C | — | B | C | — |
| CCP2 | CCP2PPS | RC1 | 0x11 | — | B | C | — | B | C | — |
| CWG | CWG1PPS | RB0 | 0x08 | — | B | C | — | B | — | D |
| DSM Carrier Low | MDCARLPPS | RA3 | 0x03 | A | — | C | A | — | — | D |
| DSM Carrier High | MDCARHPPS | RA4 | 0x04 | A | — | C | A | — | — | D |
| DSM Source | MDSRCPPS | RA5 | 0x05 | A | — | C | A | — | — | D |
| EUSART1 Receive | RX1PPS | RC7 | 0x17 | — | B | C | — | B | C | — |
| EUSART1 Clock | CK1PPS | RC6 | 0x16 | — | B | C | — | B | C | — |
| EUSART2 Receive | RX2PPS | RB7 | 0x0F | — | B | C | — | B | — | D |
| EUSART2 Clock | CK2PPS | RB6 | 0x0E | — | B | C | — | B | — | D |
| MSSP1 Clock | SSP1CLKPPS | RC3 | 0x13 | — | B | C | — | B | C | — |
| MSSP1 Data | SSP1DATPPS | RC4 | 0x14 | — | B | C | — | B | C | — |
| MSSP1 Slave Select | SSP1SSPPS | RA5 | 0x05 | A | — | C | A | — | — | D |
| MSSP2 Clock | SSP2CLKPPS | RB1 | 0x09 | — | B | C | — | B | — | D |
| MSSP2 Data | SSP2DATPPS | RB2 | 0x0A | — | B | C | — | B | — | D |
| MSSP2 Slave Select | SSP2SSPPS | RB0 | 0x08 | — | B | C | — | B | — | D |
| CLCIN0 | CLCIN0PPS | RA0 | 0x00 | A | — | C | A | — | C | — |
| CLCIN1 | CLCIN1PPS | RA1 | 0x01 | A | — | C | A | — | C | — |
| CLCIN2 | CLCIN2PPS | RB6 | 0x0E | — | B | C | — | B | — | D |
| CLCIN3 | CLCIN3PPS | RB7 | 0x0F | — | B | C | — | B | — | D |
| CLCIN4 | CLCIN4PPS | RA0 | 0x00 | A | — | C | A | — | C | — |
| CLCIN5 | CLCIN5PPS | RA1 | 0x01 | A | — | C | A | — | C | — |
| CLCIN6 | CLCIN6PPS | RB6 | 0x0E | — | B | C | — | B | — | D |
| CLCIN7 | CLCIN7PPS | RB7 | 0x0F | — | B | C | — | B | — | D |