35.10.1 HLVDCON0
| Name: | HLVDCON0 |
| Address: | 0xF2A |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN | OUT | RDY | INTH | INTL | |||||
| Access | R/W | RO | RO | R/W | R/W | ||||
| Reset | 0 | x | x | 0 | 0 |
Bit 7 – EN High/Low-voltage Detect Power Enable bit
| Value | Description |
|---|---|
| 1 | Enables the HLVD module |
| 0 | Disables the HLVD module |
Bit 5 – OUT HLVD Comparator Output bit
Bit 4 – RDY Band Gap Reference Voltages Stable Status Flag bit
| Value | Description |
|---|---|
| 1 | Indicates HLVD Module is ready and output is stable |
| 0 | Indicates HLVD Module is not ready |
Bit 1 – INTH HLVD Positive going (High Voltage) Interrupt Enable
| Value | Description |
|---|---|
| 1 | HLVDIF will be set when voltage ≥ selected detection limit (SEL) |
| 0 | HLVDIF will not be set |
Bit 0 – INTL HLVD Negative going (Low Voltage) Interrupt Enable
| Value | Description |
|---|---|
| 1 | HLVDIF will be set when voltage ≤ selected detection limit (SEL) |
| 0 | HLVDIF will not be set |