2.3 Details on Individual Family Members

Devices in the PIC18F27/47Q10 family are available in 28-pin and 40/44-pin packages. The block diagram for this device is shown in Figure 2-1.

The devices have the following differences:

  1. Program Flash Memory
  2. Data Memory SRAM
  3. Data Memory EEPROM
  4. A/D channels
  5. I/O ports
  6. Enhanced USART
  7. Input Voltage Range/Power Consumption

All other features for devices in this family are identical. These are summarized in the following Device Features table.

The pinouts for all devices are listed in the pin summary tables.

Table 2-1. Device Features
FeaturesPIC18F27Q10PIC18F47Q10
Program Memory (Bytes)

131072

131072

Program Memory (Instructions)

65536

65536

Data Memory (Bytes)

3615

3615

Data EEPROM Memory (Bytes)

1024

1024

I/O PortsA,B,C,E(1)

A,B,C,D,E

Capture/Compare/PWM Modules (CCP)22
10-Bit Pulse-Width Modulator (PWM)22
10-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator4 internal

24 external

4 internal

35 external

Packages

28-pin SPDIP
28-pin SOIC
28-pin SSOP
28-pin VQFN
28-pin QFN

40-pin PDIP
40-pin QFN
44-pin TQFP

Timers (16-/8-bit)4/34/3
Serial Communications2 MSSP,

2 EUSART

2 MSSP,

2 EUSART

Enhanced Complementary Waveform Generator (ECWG)11
Zero-Cross Detect (ZCD)11
Data Signal Modulator (DSM)11
Configurable Logic Cell (CLC)88
Peripheral Pin Select (PPS)YesYes
Peripheral Module Disable (PMD)YesYes
16-bit CRC with NVMSCANYesYes
Programmable High/Low-Voltage Detect (HLVD)YesYes
Programmable Brown-out Reset (BOR)YesYes
Resets (and Delays)POR, BOR,

RESET Instruction,

Stack Overflow,

Stack Underflow

(PWRT, OST),

MCLR, WDT

POR, BOR,

RESET Instruction,

Stack Overflow,

Stack Underflow

(PWRT, OST),

MCLR, WDT

Instruction Set75 Instructions;

83 with Extended Instruction Set enabled

75 Instructions;

83 with Extended Instruction Set enabled

Operating FrequencyDC – 64 MHzDC – 64 MHz
Note 1: PORTE contains the single RE3 read-only bit.
Figure 2-1. PIC18F27/47Q10 Family Block Diagram