48.9.4.1 CoreMark™

Core running CoreMark from different memory modes:
- Flash with cache disabled
- Flash with cache enabled

PLLA and PLLB are used to generate the required frequencies.

Table 48-57. Current Consumption
Core Clock/Main Clock (MHz)	Cache Disabled		Cache Enabled		Unit
Core Clock/Main Clock  MCK0, MCK0DIV, MCK0DIV2	AMP1	AMP2	AMP1	AMP2	Unit
200/200, 100, 200	37	29	40	37	mA
100/100, 100, 100	25	19.5	25	22	mA
50/50, 50, 50	18	13	14	13	mA

DS60001780C

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