16.4.2.4 Second Peripheral Set Reset Control

The reset of the second peripheral set is managed by RSTC_MR.CPEREN. When this bit is set to ‘1’, the reset is de-asserted. When RSTC_MR.CPEREN=0, the reset is asserted.

Note: The second peripheral set comprises peripherals driven by MCK1 and MCK1DIV. See the table “Peripheral Identifiers” for the main system bus clock driving each peripheral.

DS60001780C

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