18.9.3 TRISxy Source Selection Register

Name:

TRISxyPPS


Bit	7	6	5	4	3	2	1	0
					TRISxnPPS[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – TRISxnPPS[3:0] Pin xy PPS Tristate Control Selection

Note:

The corresponding TRISxy register bit must be set (TRISxy = 1).

Reset States:

POR = 0000

All other Resets = uuuu

Value	Name	Description
1111-1001	N/A	Reserved
1000	CLBPPS_OE[7]	CLB PPS_OE[7] controls the Tri-state/Output of the PORTpin xy⁽¹⁾
0111	CLBPPS_OE[6]	CLB PPS_OE[6] controls the Tri-state/Output of the PORTpin xy⁽¹⁾
0110	CLBPPS_OE[5]	CLB PPS_OE[5] controls the Tri-state/Output of the PORTpin xy⁽¹⁾
0101	CLBPPS_OE[4]	CLB PPS_OE[4] controls the Tri-state/Output of the PORTpin xy⁽¹⁾
0100	CLBPPS_OE[3]	CLB PPS_OE[3] controls the Tri-state/Output of the PORTpin xy⁽¹⁾
0011	CLBPPS_OE[2]	CLB PPS_OE[2] controls the Tri-state/Output of the PORTpin xy⁽¹⁾
0010	CLBPPS_OE[1]	CLB PPS_OE[1] controls the Tri-state/Output of the PORTpin xy⁽¹⁾
0001	CLBPPS_OE[0]	CLB PPS_OE[0] controls the Tri-state/Output of the PORTpin xy⁽¹⁾
0000	TRIS	TRISxy controls the Tri-state/Output of the PORTpin xy

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