1.4.1.2 PF_IOD Post-Layout Simulation

(Ask a Question)

Libero® SoC v2026.1 adds post-layout simulation support for statically delayed PolarFire® IOD resources. This support does not apply to dynamically trained PF_IOD interfaces. In this release, only post-layout gate-level functional simulation behavior is supported for the statically delayed PF_IOD resources. The PF_IOD external timing check arcs have been removed to prevent currently unsupported back-annotated timing simulation results through the IOD.

Rev: 2026.1

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.