2.1.3 Power Estimation Example

This example employs an AX1000 shift-register design with 1,080 R-cells, one C-cell, one reset input, and one LVTTL 12 mA output, with high slew.

This design uses one HCLK at 100 MHz.

The following shows the example of power estimation.

• ms = 1,080 (in a shift register—100% of R-cells are toggling at each clock cycle)
• Fs = 100 MHz
• s = 1080

  => P_HCLK = (P1 + P2 × s + P3 × sqrt[s]) × Fs = 79 mW

  and Fs = 100 MHz

  => P_R-cells = P7 × ms × Fs = 173 mW

• mc = 1 (1 C-cell in this shift-register)

  and Fs = 100 MHz

  => P_C-cells = P8 × mc × Fs = 0.14 mW

• F_pi ~ 0 MHz

  and pi = 1 (1 reset input => this is why Fpi = 0)

  => P_inputs = P9 × pi × F_pi = 0 mW

• F_po = 50 MHz

  and po = 1

  => P_outputs = PI/O × po × F_po = 27.10 mW

• No RAM/FIFO in this shift-register

  => P_memory = 0 mW

• No PLL in this shift-register

  => P_PLL = 0 mW

• P_ac = P_HCLK + P_CLK + P_R-cells + P_C-cells + P_inputs + P_outputs + P_memory + P_PLL = 276 mW
• P_dc = 7.5 mA × 1.5V = 11.25 mW
• P_total = P_dc + P_ac = 11.25 mW + 276 mW = 290.30 mW