2.8 Global Resources

One of the most important aspects of any FPGA architecture is its global resources or clocks. The Axcelerator family provides the user with flexible and easy-to-use global resources, without the limitations normally found in other FPGA architectures.

The AX architecture contains two types of global resources, the Hardwired Clock (HCLK) and Routed Clock (CLK). Every Axcelerator device is provided with four HCLKs and four CLKs for a total of eight clocks, regardless of device density.